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參數資料
| 型號： | FM93C46 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | 1024-Bit Serial CMOS EEPROM(1024位的串行CMOS EEPROM) |
| 中文描述： | 1024位串行CMOS EEPROM的（1024位的串行EEPROM中的CMOS） |
| 文件頁數： | 4/13頁 |
| 文件大小： | 114K |
| 代理商： | FM93C46 |
4
www.fairchildsemi.com
FM93C46 Rev. D.1
F
(
T
Absolute Maximum Ratings
(Note 1)
Ambient Storage Temperature
All Input or Output Voltages
with Respect to Ground
Lead Temperature
(Soldering, 10 sec.)
ESD rating
DC and AC Electrical Characteristics
V
CC
= 2.7V to 4.5V unless otherwise specified. Refer to
page 3 for V
CC
= 4.5V to 5.5V.
-65
°
C to +150
°
C
+6.5V to -0.3V
+300
°
C
2000V
Operating Conditions
Ambient Operating Temperature
FM93C46L/LZ
FM93C46LE/LZE
FM93C46LV/LZV
0
°
C to +70
°
C
-40
°
C to +85
°
C
-40
°
C to +125
°
C
Power Supply (V
CC
)
2.7V to 5.5V
Symbol
I
CCA
Parameter
Conditions
Min
Max
1
Units
mA
Operating Current
CS = V
IH
, SK=250 KHz
I
CCS
Standby Current
L
LZ (2.7V to 4.5V)
CS = V
IL
10
1
μ
A
μ
A
I
IL
I
OL
Input Leakage
Output Leakage
V
= 0V to V
CC
(Note 2)
±
1
μ
A
V
IL
V
IH
Input Low Voltage
Input High Voltage
-0.1
0.8V
CC
0.15V
CC
V
CC
+1
V
V
OL
V
OH
Output Low Voltage
Output High Voltage
I
OL
= 10
μ
A
I
OH
= -10
μ
A
0.1V
CC
V
0.9V
CC
f
SK
SK Clock Frequency
(Note 3)
0
250
KHz
t
SKH
SK High Time
1
μ
s
t
SKL
SK Low Time
1
μ
s
t
CS
Minimum CS Low Time
(Note 4)
1
μ
s
t
CSS
CS Setup Time
0.2
μ
s
t
DH
DO Hold Time
70
ns
t
DIS
DI Setup Time
0.4
μ
s
t
CSH
CS Hold Time
0
ns
t
DIH
DI Hold Time
0.4
μ
s
t
PD
Output Delay
2
μ
s
t
SV
CS to Status Valid
1
μ
s
t
DF
CS to DO in Hi-Z
CS = V
IL
0.4
μ
s
t
WP
Write Cycle Time
15
ms
Capacitance
T
A
= 25
°
C, f = 1 MHz or
250 KHz (Note 5)
Symbol
Test
Typ
Max
Units
C
OUT
C
IN
Output Capacitance
Input Capacitance
5
5
pF
pF
Note 1
:
to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect device reliability.
Stress above those listed under
“
Absolute Maximum Ratings
”
may cause permanent damage
Note 2
:
Typical leakage values are in the 20nA range.
Note 3
:
SK clock speed (minimum SK period) is determined by the interaction of several AC parameters stated
in the datasheet. Within this SK period, both t
SKH
and t
limits must be observed. Therefore, it is not
allowable to set 1/f
SK
= t
SKHminimum
+ t
SKLminimum
for shorter SK cycle time operation.
Note 4
:
CS (Chip Select) must be brought low (to V
) for an interval of t
in order to reset all internal
device registers (device reset) prior to beginning another opcode cycle. (This is shown in the opcode
diagram on the following page.)
The shortest allowable SK clock period = 1/f
(as shown under the f
parameter). Maximum
Note 5
:
This parameter is periodically sampled and not 100% tested.
AC Test Conditions
V
CC
Range
V
/V
Input Levels
0.3V/1.8V
V
/V
V
/V
Timing Level
0.8V/1.5V
I
OL
/I
OH
Timing Level
1.0V
2.7V
≤
V
≤
5.5V
(Extended Voltage Levels)
4.5V
≤
V
≤
5.5V
(TTL Levels)
±
10
μ
A
0.4V/2.4V
1.0V/2.0V
0.4V/2.4V
2.1mA/-0.4mA
Output Load: 1 TTL Gate (C
L
= 100 pF)
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