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參數資料
| 型號： | FMS6400CSX |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 消費家電 |
| 英文描述： | Dual Channel Video Drivers with Integrated Filters and Composite Video Summer |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO8 |
| 封裝： | LEAD FREE, SOIC-8 |
| 文件頁數： | 5/8頁 |
| 文件大?。?/td> | 79K |
| 代理商： | FMS6400CSX |
5
www.fairchildsemi.com
FMS6400 Rev. 1A
F
Applications Information
Functional Description
This product is a two channel monolithic continuous time video
filter designed for reconstructing the luminance and chromi-
nance signals from an S-Video D/A source. Composite video
output is generated by summing the Y and C outputs. The chip
is designed to have AC coupled inputs and will work equally well
with either AC or DC coupled outputs.
The reconstruction filters provide a 5th order Butterworth
response with group delay equalization. This provides a maxi-
mally flat response in terms of delay and amplitude. Each of the
three outputs is capable of driving 2V
pp
into a 75
load.
All channels are clamped during the sync interval to set the
appropriate minimum output dc level. With this operation the
effective input time constant is greatly reduced, which allows for
the use of small low cost coupling capacitors. The net effect is
that the input will settle to 10mV in 10ms for any DC shifts
present in the input video signal.
In most applications the input coupling capacitors are 0.1μF.
The Y and C inputs typically sink 1μA of current during active
video, which normally tilts a horizontal line by 2mV at the Y out-
put. During sync, the clamp restores this leakage current by
sourcing an average of 20μA over the clamp interval. Any
change in the coupling capacitor values will affect the amount of
tilt per line. Any reduction in tilt will come with an increase in set-
tling time.
Luminance (Y) I/O
The typical luma input is driven by either a low impedance
source of 1V
pp
or the output of a 75
terminated line driven by
the output of a current DAC. In either case, the input must be
capacitively coupled to allow the sync-detect and DC restore cir-
cuitry to operate properly.
All outputs are capable of driving 2Vpp, AC or DC coupled, into
either a single or dual video load. A single video load consists of
a series 75
impedance matching resistor connected to a ter-
minated 75
line, this presents a total of 150
of loading to the
part. A dual load would be two of these in parallel which would
present a total of 75
to the part.
Channel gain of 0dB on all channels can be selected by tying
pin 2 to ground. Channel gain of 6dB on all channels can be
selected by tying pin 2 to V
CC
. Both gain settings assume stan-
dard input video levels of 1V
pp
.
Chrominance (C) I/O
The chrominance input can be driven in the same manner as
the luminance input but is typically only a 0.7V
pp
signal.
Since the chrominance signal doesn't contain any DC content,
the output signal can be AC coupled using as small as a 0.1μF
capacitor if DC coupling is not desired.
Composite Video (CV) Output
The composite video output driver is same as the other outputs.
Layout Considerations
General layout and supply bypassing play major roles in high
frequency performance and thermal characteristics. Fairchild
offers a demonstration board, FMS6400DEMO, to use as a
guide for layout and to aid in device testing and characterization.
The FMS6400DEMO is a 4-layer board with a full power and
ground plane. For optimum results, follow the steps below as a
basis for high frequency layout:
Include 10
μ
F and 0.1
μ
F ceramic bypass capacitors
Place the 10
μ
F capacitor within 0.75 inches of the power pin
Place the 0.1
μ
F capacitor within 0.1 inches of the power pin
If using DC-coupled outputs, use a large ground plane to help
dissipate heat
Minimize all trace lengths to reduce series inductances
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