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參數資料
| 型號： | FMS6408-1 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Triple Video Filter Driver for RGB and YUV Signals |
| 中文描述： | 三視頻濾波驅動的RGB和YUV信號 |
| 文件頁數： | 5/9頁 |
| 文件大小： | 250K |
| 代理商： | FMS6408-1 |
REV. 2C August 31, 2004
5
FMS6408
DATA SHEET
Pin Configuration
Pin#
1
Pin
Y
INA
Type
Input
Description
Y (Luminance) or Green input A, must be
connected to a signal which includes sync
U or Blue input A
V or Red input A
Must be tied to ground, do not float
Y (Luminance) or Green input B, must be
connected to a signal which includes sync
U or Blue input B
V or Red input B
Mux select, A = ‘1’, B = ‘0’, must be
externally tied high or low
V or Red output
Must to be tied to ground, do not float
U or Blue output
Filter bypass, BYPASS = ‘1’, FILTER = ‘0’,
must be externally tied high or low
Y or Green output
+5V supply
2
3
4
5
U
V
GND
Y
INB
INA
Input
Input
Input
Input
INA
6
7
8
U
INB
V
INB
Input
Input
Input
IN
MUX
(A/B)
9
10
11
12
V
OUT
GND
U
OUT
BYPASS
(Bypass/Filter)
Y
OUT
V
CC
Output
Input
Output
Input
13
14
Output
Input
Functional Description
Introduction
This product is a three channel monolithic continuous time
video filter designed for reconstructing YUV, YC CV or
RGB signals from a video D/A source. Inputs should be AC
coupled while outputs can be either AC or DC coupled.
The reconstruction filters approximate a 5th order Butter-
worth response optimized for minimum overshoot and flat
group delay. This provides a maximally flat response in
terms of delay and amplitude. Each of the three outputs is
capable of driving 2V
pp
into 75
loads.
All channels are clamped during the sync interval to set the
appropriate dc output level. Sync tip clamping greatly reduces
the effective input time constant allowing the use of small
low cost input coupling capacitors. The input will settle to
10mV in 2ms for typical DC shifts present in the video signal.
In most applications the input coupling capacitors are 0.1
μ
F.
The inputs typically sink 1uA of current during active video.
For YUV signals, this translates into a 2mV tilt in a horizon-
tal line at the Y output. During sync, the clamp restores this
leakage current by sourcing an average of 20
μ
A over the
clamp interval. Any change in the coupling capacitor values
will affect the amount of tilt per line. Any reduction in tilt
will come with an increase in settling time.
Sync processing is based on the Y/G input channel in all
operating modes.
Inputs
The inputs will typically be driven by either a low impedance
source of 1V
pp
or the output of a 75
terminated line driven
by the output of a current DAC. In either case, the inputs
must be capacitively coupled to allow the sync-detect and
DC restore circuitry to operate properly.
Outputs
The outputs are low impedance voltage drivers which can
handle either a single or dual load. A single load consists of
a 75
series termination resistor feeding a 75
terminated
line for a total load at the part of 150
. Even when two loads
are present (75
) the driver will produce a full 2V
pp
signal
at its output pin. The driver can also be used to drive an AC
coupled single or dual load. When driving a dual load either
output will still function if the other output connection is
inadvertently shorted providing these loads are AC coupled.
FMS6408
14-pin
TSSOP
Y
INA
V
CC
U
INA
V
INA
BYPASS
GND
Y
INB
GND
IN
MUX
(A/B)
U
INB
V
INB
Y
OUT
U
OUT
V
OUT
1
2
3
4
5
6
7
14
13
12
11
10
9
8
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