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參數(shù)資料
| 型號(hào)： | FMS7951KWCX |
| 英文描述： | Nine Distributed-Output Clock Driver |
| 中文描述： | 九分布式輸出時(shí)鐘驅(qū)動(dòng)器 |
| 文件頁(yè)數(shù)： | 1/9頁(yè) |
| 文件大?。?/td> | 72K |
| 代理商： | FMS7951KWCX |
www.fairchildsemi.com
REV. 1.0.0 1/9/01
Features
Crystal reference input
Up to 175 MHz of output frequency
Nine configurable outputs
Output enable pin
250 pS of output to output skew
300 pS of Cycle to Cycle Jitter
V
DD
Range of 3.3V ±0.2V
Commercial temperature range
Available in 32 pin LQFP
Description
FMS7950 is a high speed clock synthesizer designed for clock
multiplication applications. It uses phase locked loop technol-
ogy to generate frequencies up to 175 MHz. It has four banks
of configurable outputs.
Feedback select (FBsel) pin allows for wider range of input
frequencies. When connected low, the lower input frequency
range is selected. This provides output frequencies of up to
eight times the input (see table 3). The higher input range is
allowed when FBsel is connected high.
There are four banks of outputs where each bank has a dedi-
cated divide select (DIV_SEL). Depending on the divide
selection, the outputs are one half, one quarter, or one eighth
of the VCO speed (see table 2 for details).
REF_SEL allows selection between crystal input or a clock
driven input. Connecting PLL_EN LOW and REF_SEL
HIGH will disable the Phase locked loop when the crystal
oscillator is not used. In this mode, FMS7950 will be in
clock buffer mode where any clock applied to TCLK will be
divided down to the four output banks per Table 2. This is
ideal for system diagnostic test.
FMS7950 operates at 3.3 Volts and is available in 32 pin LQFP.
FMS7950
Clock Multiplier
Block Diagram
MUX
MUX
DIV_SEL A
X1
X2
FBsel
TCLK
DIV_SEL B
DIV_SEL C
DIV_SEL D
QA
QB
QC0
QC1
QD0
QD1
QD2
QD3
QD4
OE
PLL
XTAL
OSC
Control
Logic
PLL_EN
REF_SEL
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