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參數資料
| 型號： | FMS988AKAC140 |
| 英文描述： | Signal Conditioner |
| 中文描述： | 信號調理 |
| 文件頁數： | 1/29頁 |
| 文件大?。?/td> | 481K |
| 代理商： | FMS988AKAC140 |
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www.fairchildsemi.com
REV. 1.2.15 1/14/02
Features
108/140 Ms/s conversion rate
RGB and YP
B
444 and 422 output timing
Adjustable Gain and offset
Internal Reference Voltage
I
C/SMBus compatible Serial Port
100-pin package
P
R
clamps
2
Applications
YP
Projectors
TV sets
B
P
R
Digitizers
Description
As a fully integrated graphics interface, the FMS9875 can
digitize RGB or YP
B
P
R
video signals at resolutions up to
1280 x 1024 with 75 Hz refresh rate. Compatible video
formats include NTSC-601, PAL-601, SMPTE 293M,
SMPTE 296M and SMPTE 274M.
The ADC sampling clock can be derived from either an
external source or from incoming horizontal sync using the
internal PLL. Setup and control is via registers accessible
through an SMBus/I
C compatible serial port.
2
Input amplitude range is 500–1000mV with either DC or AC
coupling. AC coupled inputs can be clamped to program-
mable midpoint/bottom levels or to external reference levels
using either internal or externally generated clamp timing.
Common to the three channels are clamp pulses, a bandgap
reference voltage and clocks derived from the HSYNC PLL
or an external clock source. Digital data output levels are
2.5–3.3V CMOS compliant.
Power is derived from a single +3.3 Volt power supply. Package
is a low cost 100-lead MQFP. Performance specifications are
guaranteed over 0°C to 70°C.
Product Number
FMS9875KAC100
FMS9875KAC140
Speed
108 Ms/s
140 Ms/s
Block Diagram
Bottom
Clamp
A/D
A/D
A/D
Gain &
Offset
Bottom/
Midpoint
Clamp
Bottom/
Midpoint
Clamp
Gain &
Offset
Gain &
Offset
444/422
444/422
DGY
7-0
DBP
7-0
DRP
7-0
GY
IN
GY
REF
BP
IN
BP
REF
RP
IN
RP
REF
SYNC
Stripper
Timing
Generator
ACS
IN
DCS
OUT
DCK
DCK
HSOUT
VREFIN
VREFOUT
Reference
ICLAMP
ICLAMP
SCK
A
0
A
1
Control
SDA
SCL
PWRDN
PLL
HSIN
COAST
LPF
XCK
PXCK
HS
INVSCK
CLAMP
FMS9875
GBR YP
Triple 8-Bit, 108/140 MHz A/D Converter with Clamps and PLL
B
P
R
Graphics Digitizer
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