- 您現在的位置：買賣IC網 > PDF目錄375873 > FPD87392BXB (National Semiconductor Corporation) +3.3V TFT-LCD Timing Controller with Dual LVDS Inputs/Dual RSDS⑩ Outputs for TFT-LCD Monitor and Notebook (SXGA/SXGA+/UXGA) PDF資料下載
參數資料
| 型號： | FPD87392BXB |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | +3.3V TFT-LCD Timing Controller with Dual LVDS Inputs/Dual RSDS⑩ Outputs for TFT-LCD Monitor and Notebook (SXGA/SXGA+/UXGA) |
| 中文描述： | 3.3 TFT - LCD的雙LVDS輸入定時控制器/雙⑩輸出區特別職務隊的TFT - LCD顯示器和筆記本電腦（SXGA / SXGA / UXGA）下 |
| 文件頁數： | 7/30頁 |
| 文件大小： | 1980K |
| 代理商： | FPD87392BXB |
第1頁第2頁第3頁第4頁第5頁第6頁當前第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁
AC Electrical Characteristics
T
A
= 0C to 70C, V
DD
= 3.0V to 3.6V, I
PI
= 100 μA (Unless otherwise specified)
LVDS Data Input
Symbol
Parameter
Conditions
Min
Max
10
Units
ms
RPLLS
RSKM
FPD-Link Receiver Phase Lock Loop Wake-up Time
RxIN Skew Margin (Note 2) and (
Figure 7
)
V
DD
= 3.3V,
CLK = 85 MHz
240
ps
Note 2:
Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account transmitter pulse positions (min
and max) and the receiver input setup and hold time (internal data sampling window: RSPOS). This margin allows for LVDS interconnect skew, inter-symbol
interference (both dependent on type and length of cable), and source clock (FPD-Link Transmitter TxCLK IN) jitter. The specified RSKM minimum assumes a
TPPOS max of 200 ps.
RSKM = cable skew (type, length) + source clock jitter (cycle to cycle) + remaining margin for data sampling (
≥
0)
This parameter is guaranteed by design. The limits are based on statistical analysis of the device performance over PVT (Process, Voltage, Temperature) range.
20104306
Acronyms:
RSKM
TPPOS
RSPOS
SW
Receiver Skew Margin
Transmitter Pulse Position
Receiver Strobe Position
Strobe Width
Definitions:
SW:
RSKM:
Cable Skew: Typically 10 ps 40 ps per foot.
Setup and Hold Time (Internal data sampling window)
Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) + Remaining margin for data sampling (
≥
0)
FIGURE 7. FPD-Link Receiver Input Skew Margin
20104307
FIGURE 8. Ideal Strobe Position for LVDS Input
F
www.national.com
7
相關PDF資料 |
PDF描述 |
|---|---|
| FPD94128 | 528-Ch Small Format a-Si AMLCD Controller / Column Driver with Integrated Frame Buffer |
| FPF2000 | IntelliMAX⑩ Advanced Load Management Products |
| FPF2001 | IntelliMAX⑩ Advanced Load Management Products |
| FPF2002 | IntelliMAX⑩ Advanced Load Management Products |
| FPF2003 | IntelliMAX⑩ Advanced Load Management Products |
相關代理商/技術參數 |
參數描述 |
|---|---|
| FPD87392BXBVQ | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:+3.3V TFT-LCD Timing Controller with Dual LVDS Inputs/Dual RSDS⑩ Outputs for TFT-LCD Monitor and Notebook (SXGA/SXGA+/UXGA) |
| FPD87393AMCVS/NOPB | 制造商:Texas Instruments 功能描述: |
| FPD92211A E WAF | 制造商:Texas Instruments 功能描述: |
| FPD92211SPX/NOPB | 制造商:Texas Instruments 功能描述: |
| FPD92220SNX/J7001650 | 制造商:Texas Instruments 功能描述: |
發布緊急采購，3分鐘左右您將得到回復。