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參數資料
| 型號： | FR65E |
| 廠商： | Fujitsu Limited |
| 英文描述： | 32-Bit Microcontroller |
| 中文描述： | 32位微控制器 |
| 文件頁數： | 8/87頁 |
| 文件大小： | 369K |
| 代理商： | FR65E |
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MB91307B
8
(Continued)
Pin no.
Pin name
I/O
circuit type
Description
49
DREQ1
F
DREQ1: DMA external transfer request input. When selected as a DMA
startup source, this input is in use at all times, so that output from other
functions must be stopped unless used intentionally.
PB3: General purpose input/output port.
DACK1: DMA external transfer request acknowledge output. This
function is valid when the DMA transfer request acknowledge output
setting is enabled.
PB4: General purpose input/output port. This function is enabled when
the DNA transfer request acknowledge output setting is disabled.
DEOP1: DMA external transfer end output. This function is valid when
the DMA external transfer end output setting is enabled.
DSTP1: DMA external transfer stop input. This function is valid when the
DMA external transfer stop input setting is enabled.
PB5: General purpose input/output port. This function is valid when the
DMA external transfer end output selection and the DMA external
transfer stop input selection are disabled.
Clock (oscillator) output
Clock (oscillator) input
IOWR: Write strobe output for DMA fly-by transfer. This function is valid
when the DMA fly-by transfer write strobe output setting is enabled.
PB6: General purpose input/output port. This function is valid when the
DMA fly-by transfer write strobe output setting is disabled.
IORD: Read strobe output for DMA fly-by transfer. This function is valid
when the DMA fly-by transfer read strobe output setting is enabled.
PB7: General purpose input/output port. This function is valid when the
DMA fly-by transfer read strobe output setting is disabled.
CS0: Chip select output. This function is valid when the chip select 0
output setting is enabled.
PA1: General purpose input/output port. This function is valid when the
chip select 0 output setting is disabled.
CS1: Chip select output. This function is valid when the chip select 1
output setting is enabled.
PA1: General purpose input/output port. This function is valid when the
chip select 1 output setting is disabled.
CS2: Chip select output. This function is valid when the chip select 2
output setting is enabled.
PA2: General purpose input/output port. This function is valid when the
chip select 2 output setting is disabled.
CS3: Chip select output. This function is valid when the chip select 3
output setting is enabled.
PA3: General purpose input/output port. This function is valid when the
chip select 3 output setting is disabled.
PB3
50
DACK1
F
PB4
51
DEOP1
F
DSTP1
PB5
53
54
X1
X0
A
56
IOWR
F
PB6
57
IORD
F
PB7
58
CS0
F
PA1
59
CS1
F
PA1
60
CS2
F
PA2
61
CS3
F
PA3
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