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參數資料
| 型號： | FSDM101 |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 穩壓器 |
| 英文描述： | Green Mode Fairchild Power Switch (FPSTM) |
| 中文描述： | 0.85 A SWITCHING REGULATOR, PDIP8 |
| 封裝： | MS-001BA, DIP-8 |
| 文件頁數： | 11/14頁 |
| 文件大小： | 542K |
| 代理商： | FSDM101 |
FSDM101
11
Figure 7. Protection Block
4.1 Over Load Protection (OLP) :
Overload is a load cur-
rent that exceeds a pre-set level due to an abnormal situation.
If this occurs, the protection circuit should be triggered to
protect the SMPS. It is possible that a short term load tran-
sient can occur under normal operation. If this occurs, the
system should not shut down. In order to avoid false shut-
downs, the over load protection circuit is designed to trigger
after a delay. Therefore the device can discriminate between
transient overloads and true fault conditions. The device is
pulse-by-pulse current limited and therefore, for a given
input voltage, the maximum input power is limited. If the
load tries to draw more than this, the output voltage will drop
below its set value. This reduces the opto-coupler LED cur-
rent, which in turn, will reduce the photo-transistor current.
Therefore, the 400uA current source will charge the feed-
back pin capacitor, Cfb, and the feedback voltage, Vfb, will
increase. The input to the feedback comparator is clamped at
around 3.8V. Therefore, once Vfb reaches 3.8V, the device is
switching at maximum power. At this point the 400uA cur-
rent source is blocked and the 2.5uA source continues to
charge Cfb. Once Vfb reaches 4.5V, switching stops. There-
fore the shutdown delay time is set by the time required to
charge Cfb from 3.8V to 4.5V with 2.5uA, as shown in Fig-
ure 8.
4.2 Thermal Shutdown (TSD) :
The Sense FET and the
control IC are assembled in one package. This makes it easy
for the control IC to detect the temperature of the Sense FET.
When the temperature exceeds approximately 145
°
C, ther-
mal shutdown is activated.
Figure 8. Over Load Protection Delay
5. Soft Start
: The FPS has an internal soft start circuit that
increases the drain current limit together with the MOSFET
current slowly after it starts up. The soft start time is typi-
cally 15msec as shown in Figure 9.
It progressively
increases during the start-up phase. The pulse width to the
power switching devices is progressively increased to estab-
lish the correct working conditions for transformers, induc-
tors, and capacitors. The voltage on the output capacitors is
progressively increased with the intention of smoothly estab-
lishing the required output voltage. Consequently it prevents
transformer saturation and stress on the secondary diodes.
Figure 9. Internal Soft Start
OSC
4
Vfb
S
R
Q
GATE
DRIVER
FSDM101
OLP, TSD
Protection Block
2.5uA
400uA
RESET
Vth 4.5V
OLP
+
-
TSD
S
R
Q
A/R
Cfb
R
Vfb
t
3.8V
OLP
4.5V
t1
t3
t1<<t2, t3
t1 = -1/RC
Χ
ln( 1-v(t1)/R ) v(t1)=3.8V
t2 = C
Χ
[v(t1+t2)-v(t1)]
Χ
Idelay
t2
FPS Switching Area
Idelay (5uA) charges Cfb
IC Reset
2mS
7steps
0.31A
0.75A
t
Drain current
[A]
0.34A
0.37A
0.40A
0.43A
0.46A
0.49A
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