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參數資料
| 型號： | FSL9130R4 |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | JFETs |
| 英文描述： | 5A, -100V, 0.680 Ohm, Rad Hard, SEGR Resistant, P-Channel Power MOSFETs |
| 中文描述： | 5 A, 100 V, 0.68 ohm, P-CHANNEL, Si, POWER, MOSFET, TO-205AF |
| 封裝： | HERMETIC SEALED, METAL CAN, TO-205AF, 3 PIN |
| 文件頁數： | 6/8頁 |
| 文件大小： | 45K |
| 代理商： | FSL9130R4 |
3-178
Screening Information
Screening is performed in accordance with the latest revision in effect of MIL-S-19500, (Screening Information Table).
Delta Tests and Limits (JANTXV Equivalent, JANS Equivalent)
T
C
= 25
o
C, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MAX
UNITS
Gate to Source Leakage Current
I
GSS
V
GS
=
±
20V
±
20 (Note 7)
nA
Zero Gate Voltage Drain Current
I
DSS
V
DS
= 80% Rated Value
±
25 (Note 7)
μ
A
Drain to Source On Resistance
r
DS(ON)
T
C
= 25
o
C at Rated I
D
±
20% (Note 8)
Gate Threshold Voltage
V
GS(TH)
I
D
= 1.0mA
±
20% (Note 8)
V
NOTES:
7. Or 100% of Initial Reading (whichever is greater).
8. Of Initial Reading.
Screening Information
TEST
JANTXV EQUIVALENT
JANS EQUIVALENT
Gate Stress
V
GS
= -30V, t = 250
μ
s
V
GS
= -30V, t = 250
μ
s
Pind
Optional
Required
Pre Burn-In Tests (Note 9)
MIL-S-19500 Group A,
Subgroup 2 (All Static Tests at 25
o
C)
MIL-S-19500 Group A,
Subgroup 2 (All Static Tests at 25
o
C)
Steady State Gate
Bias (Gate Stress)
MIL-STD-750, Method 1042, Condition B
V
GS
= 80% of Rated Value,
T
A
= 150
o
C, Time = 48 hours
MIL-STD-750, Method 1042, Condition B
V
GS
= 80% of Rated Value,
T
A
= 150
o
C, Time = 48 hours
Interim Electrical Tests (Note 9)
All Delta Parameters Listed in the Delta Tests
and Limits Table
All Delta Parameters Listed in the Delta Tests
and Limits Table
Steady State Reverse
Bias (Drain Stress)
MIL-STD-750, Method 1042, Condition A
V
DS
= 80% of Rated Value,
T
A
= 150
o
C, Time = 160 hours
MIL-STD-750, Method 1042, Condition A
V
DS
= 80% of Rated Value,
T
A
= 150
o
C, Time = 240 hours
PDA
10%
5%
Final Electrical Tests (Note 9)
MIL-S-19500, Group A, Subgroup 2
MIL-S-19500, Group A,
Subgroups 2 and 3
NOTE:
9. Test limits are identical pre and post burn-in.
Additional Screening Tests
PARAMETER
SYMBOL
TEST CONDITIONS
MAX
UNITS
Safe Operating Area
SOA
V
DS
= -80V, t = 10ms
1.43
A
Unclamped Inductive Switching
I
AS
V
GS(PEAK)
= -15V, L = 0.1mH
15
A
Thermal Response
V
SD
t
H
= 100ms; V
H
= -25V; I
H
= 1A
125
mV
Thermal Impedance
V
SD
t
H
= 500ms; V
H
= -25V; I
H
= 1A
250
mV
FSL9130D, FSL9130R
相關PDF資料 |
PDF描述 |
|---|---|
| FSL9130D | 5A, -100V, 0.680 Ohm, Rad Hard, SEGR Resistant, P-Channel Power MOSFETs |
| FSL9130R | 5A, -100V, 0.680 Ohm, Rad Hard, SEGR Resistant, P-Channel Power MOSFETs |
| FSL913A0R3 | 7A, -100V, 0.300 Ohm, Rad Hard, SEGR Resistant, P-Channel Power MOSFETs |
| FSL913A0D1 | 7A, -100V, 0.300 Ohm, Rad Hard, SEGR Resistant, P-Channel Power MOSFETs |
| FSL913A0D | 7A, -100V, 0.300 Ohm, Rad Hard, SEGR Resistant, P-Channel Power MOSFETs |
相關代理商/技術參數 |
參數描述 |
|---|---|
| FSL913A0D | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:7A, -100V, 0.300 Ohm, Rad Hard, SEGR Resistant, P-Channel Power MOSFETs |
| FSL913A0D1 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:7A, -100V, 0.300 Ohm, Rad Hard, SEGR Resistant, P-Channel Power MOSFETs |
| FSL913A0D3 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:7A, -100V, 0.300 Ohm, Rad Hard, SEGR Resistant, P-Channel Power MOSFETs |
| FSL913A0R | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:7A, -100V, 0.300 Ohm, Rad Hard, SEGR Resistant, P-Channel Power MOSFETs |
| FSL913A0R1 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:7A, -100V, 0.300 Ohm, Rad Hard, SEGR Resistant, P-Channel Power MOSFETs |
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