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參數(shù)資料
| 型號(hào)： | FSTU6800QSC |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | 10-Bit Bus Switch with Pre-Charged Outputs and −2V Undershoot Hardened Circuit (UHC) Protection |
| 中文描述： | CBT/FST/QS/5C/B SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDSO24 |
| 封裝： | 0.150 INCH, MO-137, QSOP-24 |
| 文件頁數(shù)： | 3/5頁 |
| 文件大小： | 181K |
| 代理商： | FSTU6800QSC |
3
www.fairchildsemi.com
F
AC Electrical Characteristics
Note 6:
This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical On
resistance of the switch and the 50 pF load capacitance, when driven by an ideal voltage the source (zero output impedance).
Capacitance
(Note 7)
Note 7:
T
A
=
+
25
°
C, f
=
1 MHz, Capacitance is characterized but not tested.
AC Loading and Waveforms
Note:
Input driven by 50
source terminated in 50
, RU
=
RD
=
500
Note:
C
L
includes load and stray capacitance, C
L
=
50 pF
Note:
Input PRR
=
1.0 MHz, t
W
=
500 nS
FIGURE 1. AC Test Circuit
FIGURE 2. AC Waveforms
Symbol
Parameter
T
=
40
°
C to
+
85
°
C,
C
L
=
50 pF, RU
=
RD
=
500
V
CC
=
4.5
–
5.5V
Min
Max
0.25
Units
Conditions
Figure No.
V
CC
=
4.0V
Min
Max
0.25
t
PHL
,t
PLH
Prop Delay Bus to Bus (Note 6)
ns
V
I
=
OPEN
Figure 1
Figure 2
t
PZH
Output Enable Time
7.0
30.0
35.0
ns
V
=
OPEN
BiasV
=
GND
V
=
7V
BiasV
=
3V
V
=
OPEN
BiasV
=
GND
V
=
7V
BiasV
=
3V
Figure 1
Figure 2
t
PZL
7.0
30.0
35.0
ns
t
PHZ
Output Disable Time
1.0
6.1
6.5
ns
Figure 1
Figure 2
t
PLZ
1.0
7.3
6.8
ns
Symbol
Parameter
Typ
Max
Units
Conditions
C
IN
Control Pin Input Capacitance
3
pF
V
CC
=
5.0V
C
I/O
Input/Output Capacitance
5
pF
V
CC
, OE
=
5.0V
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