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參數(shù)資料
| 型號： | FSTUD32450G |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Configurable 4-Bit to 40-Bit Bus Switch with -2V Undershoot Protection and Selectable Level Shifting |
| 中文描述： | CBT/FST/QS/5C/B SERIES, QUAD 10-BIT DRIVER, TRUE OUTPUT, PBGA114 |
| 封裝： | 5.50 MM, PLASTIC, MO-205, FBGA-114 |
| 文件頁數(shù)： | 10/13頁 |
| 文件大小： | 495K |
| 代理商： | FSTUD32450G |
www.fairchildsemi.com
10
F
AC Electrical Characteristics
Note 9:
This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical On
Resistance of the switch and the 50pF load capacitance, when driven by an ideal voltage source (zero output impedance).
AC Electrical Characteristics: Translating Diode
Note 10:
This parameter is guaranteed by design but is not tested. This bus switch contributes no propagation delay other than the RC delay of the typical
On Resistance of the switch and the 50pF load capacitance, when driven by an ideal voltage source (zero output impedance).
Capacitance
(Note 11)
Note 11:
T
A
=
+
25
°
C, f
=
1 MHz, Capacitance is characterized but not tested.
Symbol
Parameter
T
A
=
40
°
C to
+
85
°
C,
C
L
=
50pF, RU
=
RD
=
500
V
CC
=
4.5 – 5.5V
Min
Max
0.25
Units
Conditions
Figure
V
CC
=
4.0V
Min
(S
2
=
S
5
=
0V)
Number
Max
0.25
t
PHL
, t
PLH
Propagation Delay Bus-to-Bus
(Note 9)
Output Enable Time
ns
V
I
=
OPEN
Figures
2, 3
Figures
2, 3
t
PZH
, t
PZL
1.5
6.5
7.0
ns
V
I
=
7V for t
PZL
V
I
=
OPEN for t
PZH
V
I
=
7V for t
PLZ
V
I
=
OPEN for t
PHZ
V
I
=
7V for t
PZL
V
I
=
OPEN for t
PZH
V
I
=
7V for t
PLZ
V
I
=
OPEN for t
PHZ
t
PHZ
, t
PLZ
Output Disable Time
1.5
6.7
7.2
ns
Figures
2, 3
t
PZH
, t
PZL
S
el
(S
0, 1
) to Output Enable Time
1.5
7.0
7.5
ns
Figures
2, 3
t
PHZ
, t
PLZ
S
el
(S
0, 1
) to Output Disable Time
1.5
7.5
7.7
ns
Figures
2, 3
Symbol
Parameter
T
A
=
40
°
C to
+
85
°
C,
C
L
=
50pF, RU
=
RD
=
500
V
CC
=
4.5 – 5.5V
Min
Units
Conditions
(S
2
=
S
5
=
V
CC
)
Figure
Number
Max
0.25
t
PHL
, t
PLH
Propagation Delay Bus-to-Bus (Note
10)
Output Enable Time
ns
V
I
=
OPEN
Figures
2, 3
Figures
2, 3
t
PZH
, t
PZL
1.5
10.0
ns
V
I
=
7V for t
PZL
V
I
=
OPEN for t
PZH
V
I
=
7V for t
PLZ
V
I
=
OPEN for t
PHZ
V
I
=
7V for t
PZL
V
I
=
OPEN for t
PZH
V
I
=
7V for t
PLZ
V
I
=
OPEN for t
PHZ
t
PHZ
, t
PLZ
Output Disable Time
1.5
9.0
ns
Figures
2, 3
t
PZH
, t
PZL
S
el
(S
0, 1
) to Output Enable Time
1.5
11.0
ns
Figures
2, 3
t
PHZ
, t
PLZ
S
el
(S
0, 1
) to Output Disable Time
1.5
10.0
ns
Figures
2, 3
Symbol
Parameter
Typ
Max
Units
Conditions
C
IN
Control Pin Input Capacitance
4
pF
V
CC
=
5.0V, V
IN
=
0V
C
I/O
Input/Output Capacitance
“
OFF State
”
8
pF
V
CC
, OE
=
5.0V, V
IN
=
0V
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