- 您現在的位置：買賣IC網 > PDF目錄375950 > FT232RQ (Electronic Theatre Controls, Inc.) Incorporating Clock Generator Output and FTDIChip-ID Security Dongle PDF資料下載
參數資料
| 型號： | FT232RQ |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Incorporating Clock Generator Output and FTDIChip-ID Security Dongle |
| 中文描述： | 納入時鐘發生器輸出和FTDIChip標識安全適配器 |
| 文件頁數： | 5/29頁 |
| 文件大小： | 471K |
| 代理商： | FT232RQ |
第1頁第2頁第3頁第4頁當前第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁
FT232R USB UART I.C. Datasheet Version 1.04
Future Technology Devices International Ltd. 2005
Page 5
3. Block Diagram
3.1 Block Diagram (Simplified)
Figure 1 - FT232R Block Diagram
3.2 Functional Block Descriptions
3.3V LDO Regulator -
The 3.3V LDO Regulator generates the 3.3V reference voltage for driving the USB transceiver
cell output buffers. It requires an external decoupling capacitor to be attached to the 3V3OUT regulator output pin. It
also provides 3.3V power to the 1.5kΩ internal pull up resistor on USBDP. The main function of this block is to power
the USB Transceiver and the Reset Generator Cells rather than to power external logic. However, external circuitry
requiring a 3.3V nominal supply at a current of around than 50mA could also draw its power from the 3V3OUT pin, if
required.
USB Transceiver -
The USB Transceiver Cell provides the USB 1.1 / USB 2.0 full-speed physical interface to the USB
cable. The output drivers provide 3.3V level slew rate control signalling, whilst a differential receiver and two single
ended receivers provide USB data in, SEO and USB Reset condition detection. This Cell also incorporates internal
USB series resistors on the USB data lines, and a 1.5kΩ pull up resistor on USBDP.
USB DPLL -
The USB DPLL cell locks on to the incoming NRZI USB data and provides separate recovered clock and
data signals to the SIE block.
Internal 12MHz Oscillator -
The Internal 12MHz Oscillator cell generates a 12MHz reference clock input to the x4
Clock multiplier. The 12MHz Oscillator is also used as the reference clock for the SIE, USB Protocol Engine and
UART FIFO controller blocks
Clock Multiplier / Divider -
The Clock Multiplier / Divider takes the 12MHz input from the Oscillator Cell and
generates the 48MHz, 24MHz, 12MHz, and 6MHz reference clock signals. The 48Mz clock reference is used for the
USB DPLL and the Baud Rate Generator blocks.
Clock
Multiplier /
Divider
UART
FIFO Controller
Serial Interface
Engine
( SIE )
USB
Protocol Engine
Baud Rate
Generator
UART Controller
with
Programmable
Signal Inversion
and High Drive
3.3 Volt
LDO
Regulator
USB
Transceiver
with
Integrated
Series
Resistors
and 1.5K
Pull-up
USB DPLL
Internal
12MHz
Oscillator
48MHz
48MHz
OCSI
(optional)
OSCO
(optional)
USBDP
USBDM
3V3OUT
VCC
TXD
RXD
RTS#
CTS#
DTR#
DSR#
DCD#
RI#
CBUS0
CBUS1
CBUS2
CBUS3
CBUS4
RESET#
TEST
GND
RESET
GENERATOR
3V3OUT
FIFO TX Buffer
128 bytes
FIFO RX Buffer
256 bytes
Internal
EEPROM
To USB Transceiver Cell
24 MHz
12 MHz
6 MHz
To USB
Transceiver
Cell
VCCIO
相關PDF資料 |
PDF描述 |
|---|---|
| FT500AH-80 | Phase Control SCR 320 Amperes Avg 3000-4000 Volts |
| FT500AN-60 | PHASE CONTROL SCR |
| FT500AH-60 | Phase Control SCR 320 Amperes Avg 3000-4000 Volts |
| FT500AH-70 | Phase Control SCR 320 Amperes Avg 3000-4000 Volts |
| FT500AH | Phase Control SCR 320 Amperes Avg 3000-4000 Volts |
相關代理商/技術參數 |
參數描述 |
|---|---|
| FT232RQ-6000 | 制造商:FTDI 制造商全稱:FTDI 功能描述:USB UART IC - Single chip USB to asynchronous serial data transfer interface |
| FT232RQ-REEL | 功能描述:USB 接口集成電路 USB to Serial UART Enhanced IC QFN-32 RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| FT232RQ-TRAY | 制造商:Future Technology Devices International (FTDI Chip) 功能描述: |
| FT-23-43 | 制造商:Amidon 功能描述:Bulk |
| FT234XD-R | 制造商:Future Technology Devices International (FTDI Chip) 功能描述:IC USB SERIAL BASIC UART 12DFN 制造商:Future Technology Devices International (FTDI Chip) 功能描述:USB to Serial UART Interface |
發布緊急采購，3分鐘左右您將得到回復。