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參數(shù)資料
| 型號(hào)： | FTS250 EVAL KIT |
| 廠商： | Connor-Winfield |
| 文件頁數(shù)： | 2/8頁 |
| 文件大?。?/td> | 0K |
| 描述： | GPS TIMING MODULE EVAL BOARD |
| 產(chǎn)品培訓(xùn)模塊： | 125 Series GPS Based Timing and Synchronization Products |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計(jì)時(shí)，時(shí)鐘發(fā)生器，同步器，GPS |
| 嵌入式： | 否 |
| 已用 IC / 零件： | FTS250 |
| 主要屬性： | 1PPS/ 10 MHz 相位校準(zhǔn)功能 |
| 次要屬性： | LED 狀態(tài)指示器 |
| 已供物品： | 模塊，板，天線，線纜 |
| 其它名稱： | CW687 |
FTS250 Data Sheet #:
SG176
Page 2
Rev:
03
Date:
05/07/13
Copyright 2013 The Connor-Winfield Corp. All Rights Reserved
Specifications subject to change without notice
Functional Block Diagram
Figure 1
CPLD
ANALOG
FILTER
1 / N
LOW JITTER
VCXO
or
OCVCXO
DRIVER
&
TRANSLATION
ANTENNNA FAULT STATUS
1 PPS CMOS OUTPUT
LOCK STATUS
HOLDOVER STATUS
SERIAL OUTPUT
10 MHz CMOS
OUTPUT
10 MHz SINE
OUTPUT
DPFD
BOOT SEL
SERIAL IN
GPS REF
33
33
SMA Bulkhead
Connector
FTS250 Module
1 PPS
10 MHz REF
1 PPS REF
RESET
SYNC 1 CONTROL
SYNC 2 CONTROL
DISABLE
Wi125
(GPS Receiver)
TCXO
REFERENCE
JTAG
(Programming Only)
Pin #
Pin Name
Description
Note
1
Vcc2
3.3V±5%SupplyVoltageforPLLandInterfacingCircuitry
1
2
GND
3
*Reset
HardwareResetforGPSCircuitry.PulllowtoReset
2
4
*Disable
Open/High=EnabledOutputs.Low=DisabledOutputs
2
5
1PPSRefInput
External1PPSreference
2
6
GND
7
10MHzRefInput
ExternalLVCMOS10MHzReference
2
8
NU
UsedforFactoryProgramming
9
NU
UsedforFactoryProgramming
10
NU
UsedforFactoryProgramming
11
NU
UsedforFactoryProgramming
12
*Bootsel
NormallyHigh-PulledlowduringWi125softwareupdates
13
GND
14
Vcc1
3.3V±5%SupplyVoltageGPSTimingCircuitry
15
AntennaSupplyVoltage
2.7to13.2VInputSupplyVoltagefortheAntenna.Max45mAcontinuouscurrent
16
GND
17
RXA
RS-232CommunicationreceivesignalforUART-0
18
TXA
RS-232CommunicationtransmitsignalforUART-0
19
SYNC2Control
Lockmodeselectioncontrolsignal2
2
20
SYNC1Control
Lockmodeselectioncontrolsignal1
2
21
LockStatus
High=Unitislockedtotheselectedreference
2
22
HoldoverStatus
High=UnitisinHoldover
2
23
AntennaFaultStatus
High=FaultdetectedontheAntennaSupplyVoltage(SelfClearing)
2
24
1PPSCMOSOutput
1PPSLVCMOSOutput
2
25
GND
26
10MHzCMOSOutput
10MHzLVCMOSOutput
2
27
GND
28
10MHzSINEOutput
10MHzSineOutput(~9dBm)
Note: 1. Provide a clean supply to this pin. Connecting to Vcc1 will degrade phase noise.
2. 3.3 VDC (LVCMOS) compatible.
Pin Description
Table 1
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