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- 1 -
JULY 22, 1996
SLWS130
This document contains information which may be changed at any time without notice
GC3011 DIGITAL RESAMPLER
1.1
BLOCK DIAGRAM
A block diagram illustrating the major functions of the chip is shown in Figure 1
CV,FOZ,FIZ
Figure 1. GC3011 Block Diagram
DOUT[0:11]
12 bits
12 bits
INTERPOLATION FILTER
15 TAPS
4096 STEPS
16 SAMPLE
FIFO
I
C
CLK IN
OUTPUT CLOCK
GENERATOR
(FIXED CLOCK MODE OR
PLL AND VCO)
CLK
OUT
OCK
IN
OUT
FE
CKOUT
BYPASS
DATA
ERROR
INTERPOLATION
RATIO
DIN[0:11]
INTERPOLATION
MODES
OUTPUT MUX AND FORMAT
C
A[0:3]
C[0:8]
R/W
CS
TO ALL CIRCUITS
OUTPUT
MODES
OUTPUT
MODES
INTERPOLATION
RATIO
AND MODES
ERROR
ERROR
INTERPOLATION
RLL
MULTI-CHIP
SYNC
AND OFFSET
DC[0:11]
M/S
12 bits
DVAL
4 bits
8 bits
CK
SI
SYNC
CIRCUIT
HF
FRST
CK2X
SO
SI
SO
RESET
CVOUT
CVIN
EIN
EVAL
1.0
KEY FEATURES
80 million samples per second (MSPS) input rate
Fractional rate change down to 1/4
Synchronization logic to allow multi-chip complex
data operation.
Multiple chips can be synchronized with fixed delay
offsets.
Two chips allow rate changes up or down.
12 bit data I/O
32 bit rate control accumulator
16 sample output FIFO
15 tap linear phase interpolator
4096 interpolation steps
80% input passband (0 to 0.4F
th
the input rate
CK
)
+/- 0.1 dB passband ripple
Less than +/- 0.02 degrees rms phase jitter
-73 dB image rejection
60 dB worst case NPR
Adaptive rate change to lock the resampling
ratio to the output clock rate
PLL/VCO to generate an output clock to
match the rate change
Microprocessor interface for control, output,
and diagnostics
Built in diagnostics
2W power at 50 MHz, 5 volts
520 mW at 30 MHz, 3.3 volts
100 pin QFP package
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| GC3011-PQ | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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