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參數資料
| 型號： | GD14526-40BA |
| 英文描述： | SMPTE |
| 中文描述： | 符合SMPTE |
| 文件頁數： | 1/8頁 |
| 文件大小： | 129K |
| 代理商： | GD14526-40BA |
General Information
The GD14515 High Definition TV
Serialiser is designed for point-to-point
serial transmission systems for HDTV
signals according to SMPTE292.
The device provides a fully integrated
solution for:
u
a 1485 Mbit/s transmitter with on-chip
clock multiplying Phase Lock Loop
u
20:1 MUX
u
Scrambler
u
NRZI encoder
u
Cable driver.
GD14515 multiplexes a 20 bit parallel
interface into a single output data stream,
using a separate reference clock or the
clock following the 20 bit data.
The on-chip PLL circuit provides internal
clock synchronisation and consists of:
u
a Phase/Frequency Comparator
u
a Lock Detect Circuit
u
a Tristateable Charge Pump
u
a wide tuning range VCO.
The VCO centre frequency is determined
by the REFCK multiplied by 20. The loop
filter time constant is determined by an
external RC filter, allowing the user to
control the loop characteristics.
The multiplexed data stream is output by
two independent Open Collector 75
cable drivers each with a sink capability
of 30 mA. The cable driver current may
be adjusted in the range 20 mA - 30 mA
by the current control pin (CIN). The out-
put can be configured as a 50
differen-
tial PECL output to drive an optical
transmitter module.
The GD14515 is packaged in a 68 pin
leaded Multi Layer Ceramic (MLC) pack-
age with cavity down for easy cooling.
Preliminary
Features
l
Nominal data-rate 1485 Mbit/s NRZI.
l
Two operating ranges:
–
1.2 -1.5 Gbit/s
–
300 - 375 Mbit/s
l
Jitter in accordance with SMPTE292.
l
Complete Clock Multiplier on-chip.
l
PLL Lock Detect Output.
l
Two independent differential Open
Collector 75
cable drivers with
external termination resistors.
l
Supply operation: 5 V and 3.3 V.
l
Power dissipation: 1.2 W typ.
l
68 pin Multi Layer Ceramic (MLC)
leaded package with transmission
lines.
Applications
l
HDTV Studio equipment.
HDTV
Serialiser
GD14515
D
PFC
MUX
/20
Clock
Divide
/4
Divide
VCO
NRZI
Scramble
Phase
Ctrl.
V
LD
U
R
D
U
D
SOP1
SOP2
SON1
SON2
CIP1
CIP2
CKOUT
VCC
VCCO
VCCA
V3V3A
V3V3
VEE
DIN0
CPH0
CPH1
TCK
TCKN
REFCK
REFCN
DEN
VCTL
TCKEN
DIN19
PAR
SEN
NLDET
PFCO
NEN
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