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參數(shù)資料
| 型號： | GMM27333230ANTG-7K |
| 英文描述： | x72 SDRAM Module |
| 中文描述： | x72內(nèi)存模塊 |
| 文件頁數(shù)： | 1/14頁 |
| 文件大小： | 169K |
| 代理商： | GMM27333230ANTG-7K |
Description
The GMM27333230ATG is a 32M x 72bits
Synchronous Dynamic RAM MODULE
which is assembled 18 pieces of 32M x 4bits
Synchronous DRAMs in 54 pin TSOP II, 2
pieces of 16 bits Register in 48 pin TSSOP,
one clock distribution PLL in 24 pin SOP and
one 2048 bit EEPROM in 8 pin TSSOP
package mounted on a 168 pin printed circuit
board with decoupling capacitors. The
GMM27333230ATG is optimized for
application to the systems which are required
high density and large capacity such as main
memory of the computers and an image
memory systems, and to the others which are
requested compact size.
The GMM27333230ATG provides common
data inputs and outputs.
GMM27333230ATG
(Double Side)
Features
* PC100/PC66 Compatible
-8(125MHz)
-7K(PC100,2-2-2)/-7J(PC100,3-2-2)/-10K(PC66)
* 3.3V +/- 0.3V Power supply
* Maximum Clock frequency
100 / 125 MHz
* LVTTL Interface
* Burst read/write operation and burst read/
single write operation capability
* Programmable burst length ;
1, 2, 4, 8, Full page
* Programmable burst sequence
Sequential / Interleave
* Full Page burst length capability
Sequential burst
Burst stop capability
* Programmable CAS Latency ; 2, 3
* CKE power down mode
* Input / Output data masking
* 4096 Refresh Cycles / 64ms
* Auto refresh / Self refresh Capability
* Serial Presence Detect with EEPROM
Pin Name
CK0, 1, 2, 3
CKE0
S0, 2
RAS
CAS
WE
A0 ~ A11
BA0,1
REGE
DQ0 ~ 63
CB0 ~ 7
DQMB0 ~ 7
V
CC
V
SS
NC
V
REF
SDA
SCL
SA0 ~ 2
WP
DU
Clock input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Address input
Bank Address input
Register Enable
Data input / output
Check Bits
Data input / output Mask
Power for internal circuit
Ground for internal circuit
No Connect
Power Supply for Reference
Serial Data input/ output
Serial Clock
Address in EEPROM
Write Protect for SPD
Don't Use
32Mx72 bits
PC100 SDRAM Registered DIMM
based on 32Mx4 SDRAM with LVTTL, 4 banks & 4K Refresh
GMM27333230ATG
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 1.1/Dec.99
1999 Hyundai MicroElectronics
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PDF描述 |
|---|---|
| GMM27333230ANTG-8 | x72 SDRAM Module |
| GMM27333230ATG-10K | x72 SDRAM Module |
| GMM27333230ATG-75 | x72 SDRAM Module |
| GMM27333230ATG-7J | x72 SDRAM Module |
| GMM27333230ATG-7K | x72 SDRAM Module |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GMM27333230ANTG-8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 SDRAM Module |
| GMM27333230ATG-10K | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 SDRAM Module |
| GMM27333230ATG-75 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 SDRAM Module |
| GMM27333230ATG-7J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 SDRAM Module |
| GMM27333230ATG-7K | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 SDRAM Module |
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