
Fig. 1 Generic GPS receiver
The GP2000 chipset comprises the GP2015 RF front end
and the GP2021 12-channel correlator. Together with a
microprocessor and a SAW filter (both available from Mitel
Semiconductor) these two circuits form the heart of a GPS
(Global Positioning System) Receiver. This designer’s guide
provides technical information on the GP2000 chipset, on
GPS systems in general and on the GPS Architect
development kit.
The use of a maths co-processor is usually precluded for
cost reasons but may be unavoidable if, for instance, a high
solution update rate is required (many times a second).
Processor loading can be traded-off against the number of
active channels. However, retrospectively, this may have an
adverse impact on the software complexity and navigation
performance.
The familiarity of the developers with the development
platform and the suitability of the available tools for the
development of real-time embedded applications is also
important.
Memory Selection
The memory requirements of the GPS receiver should be
carefully considered since this constitutes a large portion of the
component costs. The choice of memory can be complex and
trade-offs need to be made against component costs, speeds
and power consumption. As with the choice of microprocessor,
the size of memory required by the receiver is also application
specific.
However, typical memory sizes, when considering just the
GPS software, are 256 Kbytes of ROM and 64 Kbytes of RAM.
(These figures are for a production engine: a development
system like GPS Architect uses more RAM – 512KBytes).
Memory savings by the reduction of the number of active
channels are not necessarily significant.
Some non-volatile memory (NVM) may be required for
information retention during periods of power-down. Parameters
such as time-to-first-fix (TTFF) can be substantially improved
by retaining satellite almanacs, ephemerides, reference oscillator
characteristics and other data in the NVM. Typical NVM
requirements amount to about 8 Kbytes.
The choice of RAM type may be influenced by software
throughput requirements.
Time critical portions of code may be run from fast SRAM
(zero wait state) at the expense of memory cost and power
consumption.
DOWN LINK
FRONT END
CORRELATOR
REFERENCE
OSCILLATOR
REAL TIME
CLOCK
SERIAL COMMS
LINK
MICRO-
PROCESSOR
CONTROL
LOGIC
ROM
RAM
NON-VOLATILE
MEMORY
SUBSYSTEM SELECTION ISSUES
Microprocessor Selection
It is difficult to state a minimum specification for a
microprocessor suitable for use in a GPS receiver since the
choice is influenced by many factors.
The performance requirements are dictated by the application
and functionality of the receiver as a whole and possibly by the
system of which the receiver is a part.
For volume GPS applications the trend is towards higher
levels of integration. As a consequence there is a need to share
resources with other parts of the complete system.
The microprocessor may be required to perform processing
of tasks which are not directly related to producing a position fix,
such as control of devices peripheral to the receiver.
Spare processing power, after catering for the GPS specific
tasks, is an attractive feature for providing cost reductions by
the possible removal of other microprocessors.
Normally, the microprocessor is required to perform both
integer and floating point arithmetic, although floating point
calculations will usually be constrained to the navigation solution
procedures.
PRACTICAL RECEIVER IMPLEMENTATION
A typical GPS receiver is shown in Fig. 1. From the antenna,
the signal is down-converted by the front end circuit ready for
processing by the correlator. A microprocessor controls the
receiver operation, including interfacing to any external display
or other function.
GP2000
GPS Chipset – Designer’s Guide
Supersedes Issue 1.4 in August 1996 Global Positioning Products Handbook, HB3045-1.0
MS4395-2.3 April 1998