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參數資料
| 型號： | GS1535-CFUE3 |
| 廠商： | Gennum Corporation |
| 英文描述： | GS1535 HD-LINX II-TM Multi-Rate SDI Automatic Reclocker |
| 中文描述： | GS1535的HD - LINX進程二，商標多速率SDI自動時鐘恢復器 |
| 文件頁數： | 15/22頁 |
| 文件大小： | 238K |
| 代理商： | GS1535-CFUE3 |
GS1535 Data Sheet
18557 - 8
February 2005
15 of 22
3.5 Phase Acquisition Loop — The Phase Detector
The phase detector is a digital quadrature phase detector. It indicates whether the
input data is leading or lagging with respect to a clock that is in phase with the VCO
(I-clk) and a quadrature clock (Q-clk). When the phase acquisition loop (PA loop)
is locked, the input data transition is aligned to the falling edge of I-clk and the
output data is re-timed on the rising edge of I-clk. During high input jitter conditions
(>0.25UI), Q-clk will sample a different value than I-clk. In this condition, two extra
phase correction signals will be generated which instructs the charge pump to
create larger frequency corrections for the VCO.
Figure 3-2: Phase Detector Characteristics.
When the PA loop is active, the crystal frequency and the incomming data rate are
compared. If the resultant is more that 2%, the PLL is considered to be unlocked
and the system jumps to the FA loop.
3.6 4:1 Input Mux
The 4:1 input mux allows the connection of four independent streams of video/data.
These are differential inputs (DDI[3:0] and DDI[3:0]). The active channel can be
selected via the DDI_SEL[1:0] pins.
Table 3-1
shows the input selected for a given
state at DDI_SEL[1:0].
i-PHASE ALIGNMENT
EDGE
DATA RE-TIMING
EDGE
q-PHASE ALIGNMENT
EDGE
0.25UI
0.8UI
I-clk
q-clk
INPUT DATA
WITH JITTER
RE-TIMED
OUTPUT DATA
Table 3-1: Bit Pattern for Input Select
DDI_SEL1:0]
Selected Input
00
DDI0
01
DDI1
10
DDI2
11
DDI3
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