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參數(shù)資料
| 型號： | GS73024AB-10 |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | DRAM |
| 英文描述： | Asynchronous SRAM |
| 中文描述： | 128K X 24 STANDARD SRAM, 10 ns, PBGA119 |
| 封裝： | 14 X 22 MM, 1.27 MM PITCH, FPBGA-119 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大小： | 452K |
| 代理商： | GS73024AB-10 |
t
AA
t
RC
Address
t
AC
t
LZ
t
OE
t
OLZ
CE
OE
Data Out
t
HZ
t
OHZ
Data valid
High impedance
GS73024AB
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03 12/2005
7/12
2003, GSI Technology
Read Cycle 2: WE = V
IH
Write Cycle
Parameter
Symbol
-8
-10
-12
Unit
Min
Max
Min
Max
Min
Max
Write cycle time
t
WC
8
—
10
—
12
—
ns
Address valid to end of write
t
AW
5.5
—
7
—
8
—
ns
Chip enable to end of write (CE)
t
CW
5.5
—
7
—
8
—
ns
Data set up time
t
DW
4
—
5
—
6
—
ns
Data hold time
t
DH
0
—
0
—
0
—
ns
Write pulse width
t
WP
5.5
—
7
—
8
—
ns
Address set up time
t
AS
0
—
0
—
0
—
ns
Write recovery time (WE)
t
WR
0
—
0
—
0
—
ns
Write recovery time ( CE )
t
WR1
0
—
0
—
0
—
ns
Output Low Z from end of write
t
WLZ*
2
—
3
—
3
—
ns
Write to output in High Z
t
WHZ*
—
4
—
5
—
6
ns
* These parameters are sampled and are not 100% tested
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS73024AB-10I | Asynchronous SRAM |
| GS73024AB-12 | Asynchronous SRAM |
| GS73024AB-12I | Asynchronous SRAM |
| GS73024AB-8 | Asynchronous SRAM |
| GS73024AB-8I | Asynchronous SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS73024AB-10I | 制造商:GSI Technology 功能描述:SRAM ASYNC SGL 3.3V 3MBIT 128KX24 10NS 119FBGA - Trays |
| GS73024AB-12 | 制造商:GSI Technology 功能描述:SRAM ASYNC SGL 3.3V 3MBIT 128KX24 12NS 119FBGA - Trays |
| GS73024AB-12I | 制造商:GSI Technology 功能描述:SRAM ASYNC SGL 3.3V 3MBIT 128KX24 12NS 119FBGA - Trays |
| GS73024AB-8 | 制造商:GSI Technology 功能描述:SRAM ASYNC SGL 3.3V 3MBIT 128KX24 8NS 119FBGA - Trays |
| GS73024AB-8I | 制造商:GSI Technology 功能描述:SRAM ASYNC SGL 3.3V 3MBIT 128KX24 8NS 119FBGA - Trays |
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