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參數資料
| 型號： | GS73024AB |
| 廠商： | GSI TECHNOLOGY |
| 英文描述： | Asynchronous SRAM |
| 中文描述： | 異步SRAM |
| 文件頁數： | 6/12頁 |
| 文件大?。?/td> | 452K |
| 代理商： | GS73024AB |
Read Cycle
Parameter
Symbol
-8
-10
-12
Unit
Min
Max
Min
Max
Min
Max
Read cycle time
t
RC
8
—
10
—
12
—
ns
Address access time
t
AA
—
8
—
10
—
12
ns
Chip enable access time (CE)
t
AC
—
8
—
10
—
12
ns
MUX control to output valid (V/S)
t
AV
—
8
—
10
—
12
ns
Output enable to output valid (OE)
t
OE
—
4
—
5
—
6
ns
Output hold from address change
t
OH
3
—
3
—
3
—
ns
Output hold from MUX controls change
t
OH1
3
—
3
—
3
—
ns
Chip enable to output in low Z (CE)
t
LZ*
3
—
3
—
3
—
ns
Output enable to output in low Z (OE)
t
OLZ*
0
—
0
—
0
—
ns
Chip disable to output in High Z (CE)
t
HZ*
—
4
—
5
—
6
ns
Output disable to output in High Z (OE)
t
OHZ*
—
4
—
5
—
6
ns
GS73024AB
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03 12/2005
6/12
2003, GSI Technology
AC Characteristics
* These parameters are sampled and are not 100% tested
t
AA
t
OH
t
RC
Address
Data Out
Previous Data
Data valid
Read Cycle 1: CE = OE = V
IL
, WE = V
IH
相關PDF資料 |
PDF描述 |
|---|---|
| GS73024AB-10 | Asynchronous SRAM |
| GS73024AB-10I | Asynchronous SRAM |
| GS73024AB-12 | Asynchronous SRAM |
| GS73024AB-12I | Asynchronous SRAM |
| GS73024AB-8 | Asynchronous SRAM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| GS73024AB-10 | 制造商:GSI Technology 功能描述:SRAM ASYNC SGL 3.3V 3MBIT 128KX24 10NS 119FBGA - Trays |
| GS73024AB-10I | 制造商:GSI Technology 功能描述:SRAM ASYNC SGL 3.3V 3MBIT 128KX24 10NS 119FBGA - Trays |
| GS73024AB-12 | 制造商:GSI Technology 功能描述:SRAM ASYNC SGL 3.3V 3MBIT 128KX24 12NS 119FBGA - Trays |
| GS73024AB-12I | 制造商:GSI Technology 功能描述:SRAM ASYNC SGL 3.3V 3MBIT 128KX24 12NS 119FBGA - Trays |
| GS73024AB-8 | 制造商:GSI Technology 功能描述:SRAM ASYNC SGL 3.3V 3MBIT 128KX24 8NS 119FBGA - Trays |
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