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參數資料
| 型號： | GS810CJEUE |
| 英文描述： | Analog IC |
| 中文描述： | 模擬IC |
| 文件頁數： | 1/6頁 |
| 文件大小： | 101K |
| 代理商： | GS810CJEUE |
1
2
3
GND
Reset
Output
V
cc
10/22/01
GS809C and GS810C
Microprocessor Reset Monitors
NewProduct
Description
The GS809C and 810C are system supervisor
circuits designed to monitor V
CC
in digital systems
and provide a reset signal to the host processor
when necessary. No external components are
required.
When the processor power supply voltage drops
below the reset threshold, the reset output is driven
active, in less than 40
μ
s (T
D1
). Reset is main-
tained active for a time period (T
D2
), after the V
cc
rises above the threshold voltage.
To prevent jitter, the reset threshold voltage has a
built-in hysteresis of 0.4% of V
TH
.
The GS809C has an active-low reset output, while
the GS810C has an active-high reset output. Both
devices have push/pull output drives.
The reset signal is guaranteed valid, down to
V
cc
= 1.0V.
Low supply current of 3
μ
A makes these devices
well suited for battery powered applications.They
are designed to reject fast transients from causing
false resets.
Both devices are available in a space-saving
SOT-23 package.
Features
Tight reset voltage tolerances ± 1.5%
4 reset active timeout period options
Low quiescent current: <3
μ
A
9 reset threshold options from 2.1V to 4.63V
Reset output guaranteed down to 1.0V
No external components
V
cc
Transient immunity
Wide temperature range –40°C to +85°C
V
CC
V
CC
GS809C
V
CC
Processor
Reset
Reset
Input
GND
GND
Fig. 1 – Typical Application Diagram
Pin Configuration
SOT-23 (Top View)
Applications
Computers
Battery Powered Equipment
Critical uProcessor and uController power supply
monitoring
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