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參數資料
| 型號： | GS8150F32 |
| 廠商： | GSI TECHNOLOGY |
| 英文描述： | 16Mb（512K x 32Bit）Synchronous Burst SRAM(16M位（512K x 32位）同步靜態RAM（帶2位脈沖地址計數器）) |
| 中文描述： | 16Mb的（為512k × 32位）同步突發靜態存儲器（1,600位（512k × 32的位）同步靜態隨機存儲器（帶2位脈沖地址計數器）） |
| 文件頁數： | 1/23頁 |
| 文件大小： | 456K |
| 代理商： | GS8150F32 |
Rev: 1.01 11/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
1/23
2000, Giga Semiconductor, Inc.
Preliminary
GS8150F18/32/36T-7/8/8.5/10/11
1M x 18, 512K x 32, 512K x 36
16Mb Sync Burst SRAMs
7 ns–11 ns
3.3 V V
DD
2.5 V or 3.3 V I/O
100-Pin TQFP
Commercial Temp
Industrial Temp
Features
Flow Through mode operation; Pin 14 = No Connect
3.3 V +10%/–5% core power supply
2.5 V or 3.3 V I/O supply
LBO pin for Linear or Interleaved Burst mode
Internal input resistors on mode pins allow floating mode pins
Byte Write (BW) and/or Global Write (GW) operation
Internal self-timed write cycle
Automatic power-down for portable applications
JEDEC-standard 100-lead TQFP package
-7
-7.5
Flow
Through
2-1-1-1
Curr (x18)
Curr (x32)
Curr (x36)
240
210
Functional Description
Applications
The GS8150F18/32/36T is a 18,874,368-bit (16,777,216-bit
for x32 version) high performance synchronous SRAM with a
2-bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPUs, the device now finds application in
synchronous SRAM applications, ranging from DSP main
store to networking chip set support.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Designing For Compatibility
The JEDEC standard for Burst RAMS calls for a FT mode pin
option on Pin 14. Board sites for flow through Burst RAMS
should be designed with V
SS
connected to the FT pin location
to ensure the broadest access to multiple vendor sources.
Boards designed with FT pin pads tied low may be stuffed with
GSI’s pipeline/flow through-configurable Burst RAMs or any
vendor’s flow through or configurable Burst SRAM. Boards
designed with the FT pin location tied high or floating must
employ a non-configurable flow through Burst RAM, like this
RAM, to achieve flow through functionality.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS8150F18/32/36T operates on a 3.3 V power supply. All
input are 3.3 V- and 2.5 V-compatible. Separate output power
(V
DDQ
) pins are used to decouple output noise from the
internal circuits and are 3.3 V- and 2.5 V-compatible.
-8
8
10
185
210
210
-8.5
8.5
10
185
210
210
-10
10
10
185
210
210
-11
11
15
140
160
160
Unit
ns
ns
mA
mA
mA
t
KQ
tCycle
7.0
8.5
205
240
7.5
10
185
210
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