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參數資料
| 型號： | GS8152Z18 |
| 廠商： | GSI TECHNOLOGY |
| 英文描述： | 16Mb Pipelined and Flow Through Synchronous NBT SRAM(16M位流水線式和流通型同步NBT靜態RAM) |
| 中文描述： | 16Mb的流水線和流量，通過同步唑的SRAM（1,600位流水線式和流通型同步唑靜態內存） |
| 文件頁數： | 1/39頁 |
| 文件大小： | 757K |
| 代理商： | GS8152Z18 |
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Rev: 1.01 11/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
1/39
2000, Giga Semiconductor, Inc.
Preliminary
GS8152Z18/36/72B-225/200/180/166/150/133
16Mb Pipelined and Flow Through
Synchronous NBT SRAM
225MHz
–
133MHz
3.3 V V
DD
2.5 V or 3.3 V I/O
119 and 209 BGA
Commercial Temp
Industrial Temp
Features
NBT (No Bus Turn Around) functionality allows zero wait
Read-Write-Read bus utilization; fully pin-compatible with
both pipelined and flow through NtRAM, NoBL and
ZBT SRAMs
3.3 V +10%/–5% core power supply
2.5 V or 3.3 V I/O supply
User-configurable Pipeline and Flow Through mode
ZQ mode pin for user-selectable high/low output drive
IEEE 1149.1 JTAG-compatible Boundary Scan
On-chip write parity checking; even or odd selectable
On-chip parity encoding and error detection
LBO pin for Linear or Interleave Burst mode
Pin-compatible with 2M, 4M, and 8M devices
Byte write operation (9-bit Bytes)
3 chip enable signals for easy depth expansion
ZZ Pin for automatic power-down
JEDEC-standard 119- or 209-Bump BGA package
Functional Description
The GS8152Z18/36/72B is a 16Mbit Synchronous Static
SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or
other pipelined read/double late write or flow through read/
single late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8152Z18/36/72B may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, in addition to the rising-edge-
triggered registers that capture input signals, the device
incorporates a rising edge triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge-triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
The GS8152Z18/36/72B is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
Standard 119-bump (x18 & x36) or 209-bump (x72) BGA
package.
-225 -200 -180 -166 -150 -133 Unit
7.0
8.5
205
240
325
285
285
285
2.5
4.4
350
410
570
515
470
435
Flow
Through
2-1-1-1
t
KQ
tCycle
Curr (x18)
Curr (x36)
Curr (x72)
t
KQ
tCycle
Curr (x18)
Curr (x36)
Curr (x72)
7.5
10.0
185
210
8.0
10.0
185
210
8.5
10.0
185
210
10.0
10.0
185
210
285
3.8
6.7
250
290
400
11.0
15.0
140
160
205
4.0
7.5
230
260
360
ns
ns
mA
mA
mA
ns
ns
mA
mA
mA
Pipeline
3-1-1-1
3.0
5.0
315
370
3.2
5.5
290
340
3.5
6.0
270
315
A
B
C
D
E
F
R
W
R
W
R
W
Q
A
D
B
Q
C
D
D
Q
E
Q
A
D
B
Q
C
D
D
Q
E
Clock
Address
Read/Write
Flow Through
Data I/O
Pipelined
Data I/O
Flow Through and Pipelined NBT SRAM Back-to-Back Read/Write Cycles
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