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參數(shù)資料
| 型號： | GS8161V18CD-333 |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | DRAM |
| 英文描述： | 1M x 18 and 512K x 36 18Mb Sync Burst SRAMs |
| 中文描述： | 1M X 18 CACHE SRAM, 4.5 ns, PBGA165 |
| 封裝： | 13 X 15 MM, 1 MM PITCH, FBGA-165 |
| 文件頁數(shù)： | 1/28頁 |
| 文件大小： | 584K |
| 代理商： | GS8161V18CD-333 |
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GS8161V18/36CD-333/300/250
1M x 18 and 512K x 36
18Mb Sync Burst SRAMs
333 MHz
–
250 MHz
1.8 V V
DD
1.8 V I/O
165-Bump BGA
Commercial Temp
Industrial Temp
Preliminary
Rev: 1.01 2/2005
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
1/28
2004, GSI Technology
Features
IEEE 1149.1 JTAG-compatible Boundary Scan
1.8 V +10%/–10% core power supply
1.8 V I/O supply
LBO pin for Linear or Interleaved Burst mode
Internal input resistors on mode pins allow floating mode pins
Byte Write (BW) and/or Global Write (GW) operation
Internal self-timed write cycle
Automatic power-down for portable applications
JEDEC-standard 165-bump BGA package
Pb-Free 165-bump BGA package available
Functional Description
Applications
The GS8161V18/36CD is an 18,874,368-bit high performance
synchronous SRAM with a 2-bit burst address counter. Although
of a type originally developed for Level 2 Cache applications
supporting high performance CPUs, the device now finds
application in synchronous SRAM applications, ranging from
DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW,
GW) are synchronous and are controlled by a positive-edge-
triggered clock input (CK). Output enable (G) and power down
control (ZZ) are asynchronous inputs. Burst cycles can be initiated
with either ADSP or ADSC inputs. In Burst mode, subsequent
burst addresses are generated internally and are controlled by
ADV. The burst address counter may be configured to count in
either linear or interleave order with the Linear Burst Order (LBO)
input. The Burst function need not be used. New addresses can be
loaded on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by the
user via the FT mode pin (Pin 14). Holding the FT mode pin low
places the RAM in Flow Through mode, causing output data to
bypass the Data Output Register. Holding FT high places the
RAM in Pipeline mode, activating the rising-edge-triggered Data
Output Register.
SCD Pipelined Reads
The GS8161V18/36CD is a SCD (Single Cycle Deselect)
pipelined synchronous SRAM. DCD (Dual Cycle Deselect)
versions are also available. SCD SRAMs pipeline deselect
commands one stage less than read commands. SCD RAMs begin
turning off their outputs immediately after the deselect command
has been captured in the input registers.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write control
inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High)
of the ZZ signal, or by stopping the clock (CK). Memory data is
retained during Sleep mode.
Core and Interface Voltages
The GS8161V18/36CD operates on a 1.8 V power supply. All
input are 1.8 V compatible. Separate output power (V
DDQ
) pins
are used to decouple output noise from the internal circuits and are
1.8 V compatible.
Parameter Synopsis
-333
-300
-250
Unit
Pipeline
3-1-1-1
t
KQ
tCycle
Curr
(x18)
Curr
(x32/x36)
2.5
3.0
2.5
3.3
2.5
4.0
ns
ns
375
435
335
390
280
330
mA
mA
Flow Through
2-1-1-1
t
KQ
tCycle
Curr
(x18)
Curr
(x32/x36)
4.5
4.5
5.0
5.0
5.5
5.5
ns
ns
280
335
230
270
210
240
mA
mA
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS8161V18CD-333I | 1M x 18 and 512K x 36 18Mb Sync Burst SRAMs |
| GS8161V18CGD-250 | 1M x 18 and 512K x 36 18Mb Sync Burst SRAMs |
| GS8161V18CGD-250I | 1M x 18 and 512K x 36 18Mb Sync Burst SRAMs |
| GS8161V18CGD-300 | 1M x 18 and 512K x 36 18Mb Sync Burst SRAMs |
| GS8161V18CGD-300I | 1M x 18 and 512K x 36 18Mb Sync Burst SRAMs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS8161V18CD-333I | 制造商:GSI 制造商全稱:GSI Technology 功能描述:1M x 18 and 512K x 36 18Mb Sync Burst SRAMs |
| GS8161V18CGD-250 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:1M x 18 and 512K x 36 18Mb Sync Burst SRAMs |
| GS8161V18CGD-250I | 制造商:GSI 制造商全稱:GSI Technology 功能描述:1M x 18 and 512K x 36 18Mb Sync Burst SRAMs |
| GS8161V18CGD-300 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:1M x 18 and 512K x 36 18Mb Sync Burst SRAMs |
| GS8161V18CGD-300I | 制造商:GSI 制造商全稱:GSI Technology 功能描述:1M x 18 and 512K x 36 18Mb Sync Burst SRAMs |
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