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參數(shù)資料
型號(hào)： GS816218D-133
廠商： GSI TECHNOLOGY
元件分類： DRAM
英文描述： 1M x 18, 512K x 36, 256K x 72 18Mb Sync Burst SRAMs
中文描述： 1M X 18 CACHE SRAM, 8.5 ns, PBGA165
封裝： 13 X 15 MM, 1 MM PITCH, FBGA-165
文件頁(yè)數(shù)： 30/41頁(yè)
文件大小： 980K
代理商： GS816218D-133
Tex8adx6prsi hsseiiainaeNtRcmmne o NwDsg.
all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is
still determined by its input pins.
GS816218(B/D)/GS816236(B/D)/GS816272(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 2.17 11/2004
30/41
1999, GSI Technology
JTAG Tap Controller State Diagram
Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This
occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facili-
tate testing of other devices in the scan path.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is
loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and
I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and
are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because
the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents
while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will
not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the
TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP
operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then
places the boundary scan register between the TDI and TDO pins.
EXTEST
Capture DR
0
Shift DR
Exit1 DR
Pause DR
Exit2 DR
Update DR
1
Capture IR
0
Shift IR
Exit1 IR
Pause IR
Exit2 IR
Update IR
1
Test Logic Reset
0
1
0
1
1
0
1
1
1
0
0
1
1
0
0
0
0
1
1
0
0
0
0
0
1
1
1
1
相關(guān)PDF資料
PDF描述
GS816218D-133I 1M x 18, 512K x 36, 256K x 72 18Mb Sync Burst SRAMs
GS816218D-150 1M x 18, 512K x 36, 256K x 72 18Mb Sync Burst SRAMs
GS816218D-150I 1M x 18, 512K x 36, 256K x 72 18Mb Sync Burst SRAMs
GS816218D-166 1M x 18, 512K x 36, 256K x 72 18Mb Sync Burst SRAMs
GS816236D-225I 1M x 18, 512K x 36, 256K x 72 18Mb Sync Burst SRAMs
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS816218DB-150 制造商:GSI Technology 功能描述:119 BGA - Bulk
GS816218DB-150I 制造商:GSI Technology 功能描述:119 BGA - Bulk
GS816218DB-150IV 制造商:GSI Technology 功能描述:119 BGA - Bulk
GS816218DB-150V 制造商:GSI Technology 功能描述:119 BGA - Bulk
GS816218DB-200 制造商:GSI Technology 功能描述:119 BGA - Bulk
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