- 您現在的位置：買賣IC網 > PDF目錄385316 > GS816272C-150I (GSI TECHNOLOGY) 1M x 18, 512K x 36, 256K x 72 18Mb Sync Burst SRAMs PDF資料下載
參數資料
| 型號： | GS816272C-150I |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | DRAM |
| 英文描述： | 1M x 18, 512K x 36, 256K x 72 18Mb Sync Burst SRAMs |
| 中文描述： | 256K X 72 CACHE SRAM, 7.5 ns, PBGA209 |
| 封裝： | 14 X 22 MM, 1 MM PITCH, BGA-209 |
| 文件頁數： | 13/41頁 |
| 文件大小： | 980K |
| 代理商： | GS816272C-150I |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁當前第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁
Tex8adx6prsi hsseiiainaeNtRcmmne o NwDsg.
GS816218(B/D)/GS816236(B/D)/GS816272(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 2.17 11/2004
13/41
1999, GSI Technology
Synchronous Truth Table
Operation
Address Used
State
Diagram
Key
E
1
ADSP
ADSC
ADV
W
3
DQ
4
Deselect Cycle, Power Down
None
X
H
X
L
X
X
High-Z
Read Cycle, Begin Burst
External
L
L
X
X
X
Q
Read Cycle, Begin Burst
External
L
H
L
X
F
Q
Write Cycle, Begin Burst
External
W
L
H
L
X
D
Read Cycle, Continue Burst
Next
CR
X
H
H
L
F
Q
Read Cycle, Continue Burst
Next
CR
H
X
H
L
F
Q
Write Cycle, Continue Burst
Next
CW
X
H
H
L
D
Write Cycle, Continue Burst
Next
CW
H
X
H
L
D
Read Cycle, Suspend Burst
Current
X
H
H
H
F
Q
Read Cycle, Suspend Burst
Current
H
X
H
H
F
Q
Write Cycle, Suspend Burst
Current
X
H
H
H
D
Write Cycle, Suspend Burst
Current
H
X
H
H
D
Notes:
1.
2.
3.
X = Don’t Care, H = High, L = Low
W = T (True) and F (False) is defined in the Byte Write Truth Table preceding
G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown
as “Q” in the Truth Table above).
All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish
basic synchronous or synchronous burst operations and may be avoided for simplicity.
Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See
BOLD
items above.
Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See
ITALIC
items above.
4.
5.
6.
相關PDF資料 |
PDF描述 |
|---|---|
| GS816272C-166 | 1M x 18, 512K x 36, 256K x 72 18Mb Sync Burst SRAMs |
| GS816272C-166I | 1M x 18, 512K x 36, 256K x 72 18Mb Sync Burst SRAMs |
| GS816272C-200 | 1M x 18, 512K x 36, 256K x 72 18Mb Sync Burst SRAMs |
| GS816272C-200I | 1M x 18, 512K x 36, 256K x 72 18Mb Sync Burst SRAMs |
| GS816272CC-150IV | 256K x 72 18Mb S/DCD Sync Burst SRAMs |
相關代理商/技術參數 |
參數描述 |
|---|---|
| GS816272C200 | 制造商:GSI 功能描述:New |
| GS816272CC-150 | 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 2.5V/3.3V 18MBIT 256KX72 7.5NS/3.8NS 209FBGA - Trays |
| GS816272CC-150I | 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 2.5V/3.3V 18MBIT 256KX72 7.5NS/3.8NS 209FBGA - Trays |
| GS816272CC-150IV | 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 1.8V/2.5V 18MBIT 256KX72 7.5NS/3.8NS 209FBGA - Trays |
| GS816272CC-150V | 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 1.8V/2.5V 18MBIT 256KX72 7.5NS/3.8NS 209FBGA - Trays |
發布緊急采購，3分鐘左右您將得到回復。