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參數(shù)資料
| 型號： | GS8162Z72C-200I |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | DRAM |
| 英文描述： | 18Mb Pipelined and Flow Through Synchronous NBT SRAM |
| 中文描述： | 256K X 72 ZBT SRAM, 6.5 ns, PBGA209 |
| 封裝： | 14 X 22 MM, 1 MM PITCH, BGA-209 |
| 文件頁數(shù)： | 1/38頁 |
| 文件大小： | 838K |
| 代理商： | GS8162Z72C-200I |
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GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)
18Mb Pipelined and Flow Through
Synchronous NBT SRAM
250 MHz
–
133 MHz 2.5
V or 3.3 V V
DD
2.5 V or 3.3 V I/O
119, 165, & 209 BGA
Commercial Temp
Industrial Temp
Rev: 2.21 11/2004
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
1/38
1999, GSI Technology
Features
NBT (No Bus Turn Around) functionality allows zero wait
Read-Write-Read bus utilization; fully pin-compatible with
both pipelined and flow through NtRAM, NoBL and
ZBT SRAMs
2.5 V or 3.3 V +10%/–10% core power supply
2.5 V or 3.3 V I/O supply
User-configurable Pipeline and Flow Through mode
ZQ mode pin for user-selectable high/low output drive
IEEE 1149.1 JTAG-compatible Boundary Scan
LBO pin for Linear or Interleave Burst mode
Pin-compatible with 2M, 4M, and 8M devices
Byte write operation (9-bit Bytes)
3 chip enable signals for easy depth expansion
ZZ Pin for automatic power-down
JEDEC-standard 119-, 165-, or 209-Bump BGA package
Functional Description
The GS8162Z18(B/D)/36(B/D)/72(C) is an 18Mbit
Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT,
NtRAM, NoBL or other pipelined read/double late write or
flow through read/single late write SRAMs, allow utilization
of all available bus bandwidth by eliminating the need to insert
deselect cycles when the device is switched from read to write
cycles.
Because it is a synchronous device, address, data inputs, and
read/write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8162Z18(B/D)/36(B/D)/72(C) may be configured by
the user to operate in Pipeline or Flow Through mode.
Operating as a pipelined synchronous device, in addition to the
rising-edge-triggered registers that capture input signals, the
device incorporates a rising edge triggered output register. For
read cycles, pipelined SRAM output data is temporarily stored
by the edge-triggered output register during the access cycle
and then released to the output drivers at the next rising edge of
clock.
The GS8162Z18(B/D)/36(B/D)/72(C) is implemented with
GSI's high performance CMOS technology and is available in
a JEDEC-standard 119-bump (x18 & x36), 165-bump (x18 &
x36), or 209-bump (x72) BGA package.
Parameter Synopsis
-250 -225 -200 -166 -150 -133 Unit
2.5
4.0
4.4
5.0
6.0
Pipeline
3-1-1-1
t
KQ
tCycle
Curr (x18)
Curr (x36)
Curr (x72)
Curr (x18)
Curr (x36)
Curr (x72)
2.7
3.0
3.4
3.8
6.7
4.0
7.5
ns
ns
3.3 V
280
330
n/a
275
320
n/a
255
300
n/a
250
295
n/a
230
270
350
230
265
335
200
230
300
195
225
290
185
215
270
180
210
260
165
190
245
165
185
235
mA
mA
mA
mA
mA
mA
2.5 V
Flow
Through
2-1-1-1
t
KQ
tCycle
5.5
5.5
6.0
6.0
6.5
6.5
7.0
7.0
7.5
7.5
8.5
8.5
ns
ns
3.3 V
Curr (x18)
Curr (x36)
Curr (x72)
Curr (x18)
Curr (x36)
Curr (x72)
175
200
n/a
175
200
n/a
165
190
n/a
165
190
n/a
160
180
225
160
180
225
150
170
115
150
170
115
145
165
210
145
165
210
135
150
185
135
150
185
mA
mA
mA
mA
mA
mA
2.5 V
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS8162Z18D-200I | 18Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8162Z18D-225 | 18Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8162Z18D-225I | 18Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8162Z18D-250 | 18Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8162Z18D-250I | 18Mb Pipelined and Flow Through Synchronous NBT SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS8162Z72CC-150 | 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 2.5V/3.3V 18MBIT 256KX72 7.5NS/3.8NS 209FBGA - Trays |
| GS8162Z72CC-150I | 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 2.5V/3.3V 18MBIT 256KX72 7.5NS/3.8NS 209FBGA - Trays |
| GS8162Z72CC-150IV | 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 1.8V/2.5V 18MBIT 256KX72 7.5NS/3.8NS 209FBGA - Trays |
| GS8162Z72CC-150V | 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 1.8V/2.5V 18MBIT 256KX72 7.5NS/3.8NS 209FBGA - Trays |
| GS8162Z72CGC-150I | 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 2.5V/3.3V 18MBIT 256KX72 7.5NS/3.8NS 209FBGA - Trays |
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