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參數資料
型號: GS8162Z72C
廠商: GSI TECHNOLOGY
英文描述: 18Mb Pipelined and Flow Through Synchronous NBT SRAM
中文描述: 35.7流水線和流量,通過同步唑的SRAM
文件頁數: 1/31頁
文件大小: 774K
代理商: GS8162Z72C
GS8162Z72C
18Mb Pipelined and Flow Through
Synchronous NBT SRAM
200 MHz
133 MHz
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
209-bump BGA
Commercial Temp
Industrial Temp
Rev: 2.22 11/2005
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
1/31
1999, GSI Technology
Features
NBT (No Bus Turn Around) functionality allows zero wait
Read-Write-Read bus utilization; fully pin-compatible with
both pipelined and flow through NtRAM, NoBL and
ZBT SRAMs
2.5 V or 3.3 V +10%/–10% core power supply
2.5 V or 3.3 V I/O supply
User-configurable Pipeline and Flow Through mode
ZQ mode pin for user-selectable high/low output drive
IEEE 1149.1 JTAG-compatible Boundary Scan
LBO pin for Linear or Interleave Burst mode
Pin-compatible with 2M, 4M, and 8M devices
Byte write operation (9-bit Bytes)
3 chip enable signals for easy depth expansion
ZZ Pin for automatic power-down
JEDEC-standard 209-Bump BGA package
Functional Description
The GS8162Z72C is an 18Mbit Synchronous Static SRAM.
GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other
pipelined read/double late write or flow through read/single
late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8162Z72C may be configured by the user to operate in
Pipeline or Flow Through mode. Operating as a pipelined
synchronous device, in addition to the rising-edge-triggered
registers that capture input signals, the device incorporates a
rising edge triggered output register. For read cycles, pipelined
SRAM output data is temporarily stored by the edge-triggered
output register during the access cycle and then released to the
output drivers at the next rising edge of clock.
The GS8162Z72C is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
standard 209-bump BGA package.
Parameter Synopsis
-200
3.0
5.0
-166
3.4
6.0
-150
3.8
6.7
-133
4.0
7.5
Unit
ns
ns
Pipeline
3-1-1-1
t
KQ
tCycle
Curr (x72)
Curr (x72)
t
KQ
tCycle
Curr (x72)
Curr (x72)
3.3 V
2.5 V
350
335
6.5
6.5
225
225
300
290
7.0
7.0
115
115
270
260
7.5
7.5
210
210
245
235
8.5
8.5
185
185
mA
mA
ns
ns
mA
mA
Flow Through
2-1-1-1
3.3 V
2.5 V
相關PDF資料
PDF描述
GS8162ZV72CC-150I 18Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8162ZV72CC 18Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8162ZV72CC-150 18Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8162ZV72CC-200 18Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8162ZV72CC-200I 18Mb Pipelined and Flow Through Synchronous NBT SRAM
相關代理商/技術參數
參數描述
GS8162Z72CC-150 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 2.5V/3.3V 18MBIT 256KX72 7.5NS/3.8NS 209FBGA - Trays
GS8162Z72CC-150I 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 2.5V/3.3V 18MBIT 256KX72 7.5NS/3.8NS 209FBGA - Trays
GS8162Z72CC-150IV 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 1.8V/2.5V 18MBIT 256KX72 7.5NS/3.8NS 209FBGA - Trays
GS8162Z72CC-150V 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 1.8V/2.5V 18MBIT 256KX72 7.5NS/3.8NS 209FBGA - Trays
GS8162Z72CGC-150I 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 2.5V/3.3V 18MBIT 256KX72 7.5NS/3.8NS 209FBGA - Trays
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