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參數資料
| 型號： | GS8170D18 |
| 廠商： | GSI TECHNOLOGY |
| 英文描述： | 16Mb（1M x 18Bit）DDR(Double Data Rate Read and Write mode) SRAM(16M位（1M x 18位）雙數據速率讀和寫模式靜態RAM) |
| 中文描述： | 16Mb的（100萬x 18位）DDR（雙數據速率讀寫模式）的SRAM（1,600位（100萬× 18位），雙數據速率讀和寫模式靜態內存） |
| 文件頁數： | 1/34頁 |
| 文件大小： | 870K |
| 代理商： | GS8170D18 |
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Rev: 1.01 11/2000
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
1/34
2000, Giga Semiconductor, Inc.
A
Advanced Information
GS8170D18/36B-333/300/275/250
1M x 18, 512K x 36 16Mb
DDR SRAM
333 MHz
1.8 V V
DD
1.8 V and 1.5 V I/O
209-Bump BGA
Commercial Temp
Industrial Temp
Σ
RAM
Features
Double Data Rate Read and Write mode
Observes the Sigma RAM pinout standard
1.8 V +150/–100 mV core power supply
1.5 V or 1.8 V I/O supply
Pipelined read operation.
Fully coherent read and write pipelines
Echo Clock outputs track data output drivers
ZQ mode pin for user-selectable output drive strength
2 User programmable chip enable inputs for easy depth
expansion.
IEEE 1149.1 JTAG-compatible Boundary Scan
209-bump, 14 mm x 22 mm, 1 mm bump pitch BGA package
Pin compatible with future 32M, 64M, and 128M devices
Sigma RAM Family Overview
The GS8170D18/36B
Σ
RAMs are built in compliance with the
Sigma RAM pinout standard for synchronous SRAMs. They
are 18,874,368-bit (16Mb) SRAMs. These are the first in a
family of wide, very low voltage CMOS I/O SRAMs designed
to operate at the speeds needed to implement economical high
performance networking systems.
GSI's
Σ
RAMs are offered in a number of configurations that
emulate other synchronous SRAMs, such as Burst RAMs,
NBT RAMs, Late Write, or Double Data Rate (DDR) SRAMs.
The logical differences between the protocols employed by
these RAMs hinge mainly on various combinations of address
bursting, output data registering and write cueing.
Σ
RAMs
allow a user to implement the interface protocol best suited to
the task at hand.
Functional Description
Because a Sigma RAM is a synchronous device, address, and
read/write control inputs are captured on the rising edge of the
input clock. Output Enable is the only asynchronous control
input. Output Enable can be used to override the synchronous
control of the output drivers and turn the RAM's output drivers
off at any time. Write cycles are internally self-timed and
initiated by the rising edge of the clock input. This feature
eliminates complex off-chip write pulse generation required by
asynchronous SRAMs and simplifies input signal timing. In
DDR mode the device captures Data In on both rising and
falling edges of clock and drives data on both clock edges as
well.
Because the DDR
Σ
RAM always transfers data in two halves,
A0 is internally set to 0 for the first half of each read or write
transfer, and automatically incremented to 1 for the falling
edge transfer. The address field of a DDR
Σ
RAM is always one
address pin less than the advertised index depth (e.g., the 1M x
18 has a 512k addressable index).
In Pipeline mode, an ordinary single data rate RAM
incorporates a rising-edge-riggered output register. In DDR
mode, rising- and falling-edge-triggered output registers are
employed. For read cycles, a DDR SRAM’s output data is
temporarily stored by the edge-triggered output register during
the access cycle and then released to the output drivers at the
next rising and subsequent falling edge of clock.
GS817x18/36/72B
Σ
RAMs are implemented with GSI's high
performance CMOS technology and are packaged in a 209-
bump BGA.
- 333
3.0 ns
1.5 ns
Pipeline mode
tKHKH
tKHQV
209-Bump, 14 mm x 22 mm BGA
1 mm Bump Pitch, 11 x 19 Bump Array
Bottom View
相關PDF資料 |
PDF描述 |
|---|---|
| GS8170D36 | 16Mb（512K x 36Bit）DDR(Double Data Rate Read and Write mode) SRAM(16M位（512K x 36位）雙數據速率讀和寫模式靜態RAM) |
| GS8170DD36C | 18Mb ヒ1x2Lp CMOS I/O Double Data Rate SigmaRAM |
| GS8170DD36C-200 | 18Mb ヒ1x2Lp CMOS I/O Double Data Rate SigmaRAM |
| GS8170DD36C-200I | 18Mb ヒ1x2Lp CMOS I/O Double Data Rate SigmaRAM |
| GS8170DD36C-250 | 18Mb ヒ1x2Lp CMOS I/O Double Data Rate SigmaRAM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| GS8170DW36AC-300I | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 1.8NS 209FBGA - Trays |
| GS8170DW36AC-350 | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 1.7NS 209FBGA - Trays |
| GS8170DW36AC-350I | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 1.7NS 209FBGA - Trays |
| GS8170DW36AGC-250 | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 2.1NS 209FBGA - Trays |
| GS8170DW36AGC-250I | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 2.1NS 209FBGA - Trays |
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