- 您現在的位置：買賣IC網 > PDF目錄383036 > GS8170DW36AGC-333 (GSI TECHNOLOGY) 18Mb ヒ1x1Dp CMOS I/O Double Late Write SigmaRAM PDF資料下載
參數資料
| 型號： | GS8170DW36AGC-333 |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | DRAM |
| 英文描述： | 18Mb ヒ1x1Dp CMOS I/O Double Late Write SigmaRAM |
| 中文描述： | 512K X 36 STANDARD SRAM, 1.8 ns, PBGA209 |
| 封裝： | 14 X 22 MM, 1 MM PITCH, LEAD FREE, BGA-209 |
| 文件頁數： | 1/32頁 |
| 文件大小： | 766K |
| 代理商： | GS8170DW36AGC-333 |
當前第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁
GS8170DW36/72AC-350/333/300/250
18Mb
Σ
1x1Dp CMOS I/O
Double Late Write SigmaRAM
250 MHz–350 MHz
1.8 V V
DD
1.8 V I/O
209-Bump BGA
Commercial Temp
Industrial Temp
Rev: 1.04 4/2005
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
1/32
2003, GSI Technology
Features
Double Late Write mode, Pipelined Read mode
JEDEC-standard SigmaRAM
pinout and package
1.8 V +150/–100 mV core power supply
1.8 V CMOS Interface
ZQ controlled user-selectable output drive strength
Dual Cycle Deselect
Burst Read and Write option
Fully coherent read and write pipelines
Echo Clock outputs track data output drivers
Byte write operation (9-bit bytes)
2 user-programmable chip enable inputs
IEEE 1149.1 JTAG-compliant Serial Boundary Scan
209-bump, 14 mm x 22 mm, 1 mm bump pitch BGA package
Pin-compatible with future 36Mb, 72Mb, and 144Mb
devices
Pb-Free 209-bump BGA package available
SigmaRAM Family Overview
GS8170
DW
36/72A SigmaRAMs are built in compliance with
the SigmaRAM pinout standard for synchronous SRAMs.
They are 18,874,368-bit (18Mb) SRAMs. This family of wide,
very low voltage CMOS I/O SRAMs is designed to operate at
the speeds needed to implement economical high performance
networking systems.
Σ
RAMs are offered in a number of configurations including
Late Write, Double Late Write, and Double Data Rate (DDR).
The logical differences between the protocols employed by
these RAMs mainly involve various approaches to write
cueing and data transfer rates. The
Σ
RAM
family standard
allows a user to implement the interface protocol best suited to
the task at hand.
Functional Description
Because SigmaRAMs are synchronous devices, address data
inputs and read/write control inputs are captured on the rising
edge of the input clock. Write cycles are internally self-timed
and initiated by the rising edge of the clock input. This feature
eliminates complex off-chip write pulse generation required by
asynchronous SRAMs and simplifies input signal timing.
Σ
RAMs support pipelined reads utilizing a rising-edge-
triggered output register. They also utilize a Dual Cycle
Deselect (DCD) output deselect protocol.
Σ
RAMs are implemented with high performance CMOS
technology and are packaged in a 209-bump BGA.
209-Bump, 14 mm x 22 mm BGA
1 mm Bump Pitch, 11 x 19 Bump Array
Bottom View
Parameter Synopsis
Key Fast Bin Specs
Symbol
- 350
Cycle Time
tKHKH
2.86 ns
Access Time
tKHQV
1.7 ns
相關PDF資料 |
PDF描述 |
|---|---|
| GS8170S36 | 16Mb（512K x 36Bit）Synchronous SRAM(16M位（512K x 36位）同步靜態RAM) |
| GS8170S18 | 16Mb（1M x 18Bit）Synchronous SRAM(16M位（1M x 18位）同步靜態RAM) |
| GS8170S72 | 16Mb（256K x 72Bit）Synchronous SRAM(16M位（256K x 72位）同步靜態RAM) |
| GS8180D09 | 2Mb x 9Bit Separate I/O Sigma DDR SRAM(2M x 9位獨立I/O接口雙數據速率讀和寫模式靜態ΣRAM) |
| GS8180D18 | 1Mb x 18Bit Separate I/O Sigma DDR SRAM(1M x 18位獨立I/O接口雙數據速率讀和寫模式靜態ΣRAM) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| GS8170DW36AGC-350 | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 1.7NS 209FBGA - Trays |
| GS8170DW36AGC-350I | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 1.7NS 209FBGA - Trays |
| GS8170DW36C-250 | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 2.1NS 209FBGA - Trays |
| GS8170DW36C-250I | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 2.1NS 209FBGA - Trays |
| GS8170DW72AC-250 | 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 1.8V 18MBIT 256KX72 2.1NS 209FBGA - Trays |
發布緊急采購，3分鐘左右您將得到回復。