- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄383037 > GS82032Q-133 (Electronic Theatre Controls, Inc.) 64K x 32 2M Synchronous Burst SRAM PDF資料下載
參數(shù)資料
| 型號(hào)： | GS82032Q-133 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類(lèi)： | DRAM |
| 英文描述： | 64K x 32 2M Synchronous Burst SRAM |
| 中文描述： | 64K的× 32 200萬(wàn)同步突發(fā)靜態(tài)存儲(chǔ)器 |
| 文件頁(yè)數(shù)： | 1/23頁(yè) |
| 文件大小： | 760K |
| 代理商： | GS82032Q-133 |
當(dāng)前第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)
Rev: 1.04 2/2001
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
ByteSafe is a Trademark of Giga Semiconductor, Inc. (GSI Technology).
1/23
2000, Giga Semiconductor, Inc.
Preliminary
GS82032T/Q-150/138/133/117/100/66
64K x 32
2M Synchronous Burst SRAM
150 MHz–66 MHz
9 ns–18 ns
3.3 V V
DD
3.3 V and 2.5 V I/O
TQFP, QFP
Commercial Temp
Industrial Temp
Features
FT pin for user-configurable flow through or pipeline
operation
Single Cycle Deselect (SCD) operation
3.3 V +10%/–5% core power supply
2.5 V or 3.3 V I/O supply
LBO pin for Linear or Interleaved Burst mode
Internal input resistors on mode pins allow floating mode pins
Default to Interleaved Pipeline mode
Byte Write (BW) and/or Global Write (GW) operation
Common data inputs and data outputs
Clock Control, registered, address, data, and control
Internal self-timed write cycle
Automatic power-down for portable applications
JEDEC-standard 100-lead TQFP or QFP package
-150
-138
-133
Pipeline
3-1-1-1
t
KQ
I
DD
270
245
Flow
Through
2-1-1-1
I
DD
170
120
Functional Description
Applications
The GS82032 is a 2,097,152-bit high performance
synchronous SRAM with a 2-bit burst address counter.
Although of a type originally developed for Level 2 Cache
applications supporting high performance CPUs, the device
now finds application in synchronous SRAM applications
ranging from DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enables (E
1
, E
2
, E
3
), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin/bump (Pin 14 in the TQFP, Bump
1F in the FP-BGA). Holding the FT mode pin/bump low,
places the RAM in Flow Through mode, causing output data to
bypass the Data Output Register. Holding FT high places the
RAM in Pipeline mode, activating the rising-edge-triggered
Data Output Register.
SCD Pipelined Reads
The GS82032 is an SCD (Single Cycle Deselect) pipelined
synchronous SRAM. DCD (Dual Cycle Deselect) versions are
also available. SCD SRAMs pipeline deselect commands one
stage less than read commands. SCD RAMs begin turning off
their outputs immediately after the deselect command has been
captured in the input registers.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the byte write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS82032 operates on a 3.3 V power supply and all inputs/
outputs are 3.3 V- and 2.5 V-compatible. Separate output
power (V
DDQ
) pins are used to decouple output noise from the
internal circuit.
-117
8.5
4.5
210
15
11
120
-100
10
5
180
15
12
120
-66
12.5
6
150
20
18
95
Unit
ns
ns
mA
ns
ns
mA
tCycle
6.6
3.8
7.25
4
7.5
4
240
15
10
120
tCycle
t
KQ
10.5
9
15
9.7
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS82032Q-133I | 64K x 32 2M Synchronous Burst SRAM |
| GS82032Q-138 | 64K x 32 2M Synchronous Burst SRAM |
| GS82032Q-138I | 64K x 32 2M Synchronous Burst SRAM |
| GS82032Q-150 | 64K x 32 2M Synchronous Burst SRAM |
| GS82032T-138I | .56UF/100VDC METAL POLY CAP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS82032Q-133I | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:64K x 32 2M Synchronous Burst SRAM |
| GS82032Q-138 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:64K x 32 2M Synchronous Burst SRAM |
| GS82032Q-138I | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:64K x 32 2M Synchronous Burst SRAM |
| GS82032Q-150 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:64K x 32 2M Synchronous Burst SRAM |
| GS82032Q-150I | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:64K x 32 2M Synchronous Burst SRAM |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。