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參數資料
| 型號： | GS820E32A |
| 廠商： | GSI TECHNOLOGY |
| 英文描述： | 2Mb（64K x 32Bit) Synchronous Burst SRAM(2M位（64K x 32位）同步靜態RAM（帶2位脈沖地址計數器）) |
| 中文描述： | 2MB的（64K的x 32位）同步突發靜態存儲器（200萬位（64K的× 32位）同步靜態隨機存儲器（帶2位脈沖地址計數器）） |
| 文件頁數： | 1/23頁 |
| 文件大小： | 344K |
| 代理商： | GS820E32A |
Rev: 1.04 3/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
1/23
2000, Giga Semconductor, Inc.
E
GS820E32AT/Q-150/138/133/117/100/66
64K x 32
2MSynchronous Burst SRAM
150Mhz - 66Mhz
9ns - 18ns
3.3V VDD
3.3V & 2.5V I/O
TQFP, QFP
Commercial Temp
Industrial Temp
Features
FT pin for user configurable flow through or pipelined operation.
Dual Cycle Deselect (DCD) Operation.
3.3V +10%/-5% Core power supply
2.5V or 3.3V I/O supply.
LBO pin for linear or interleaved burst mode.
Internal input resistors on mode pins allow floating mode pins.
Default to Interleaved Pipelined Mode.
Byte write (BW) and/or global write (GW) operation.
Common data inputs and data outputs.
Clock Control, registered, address, data, and control.
Internal Self-Timed Write cycle.
Automatic power-down for portable applications.
JEDEC standard 100-lead TQFP or QFP package.
-150
-138
Pipeline
3-1-1-1
t
KQ
I
DD
270mA
245mA
Flow
Through
2-1-1-1
I
DD
170mA
120mA
Functional Description
Applications
The GS820E32A is a 2,097,152 bit high performance synchronous
SRAMwith a 2 bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPU’s, the device now finds application in synchronous
SRAM applications ranging fromDSP main store to networking chip
set support.
Controls
Addresses, data I/O’s, chip enables (E
1
, E
2
, E
3
), address burst control
inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW, GW) are
synchronous and are controlled by a positive edge triggered clock
input (CK). Output enable (G) and power down control (ZZ) are
asynchronous inputs. Burst cycles can be initiated with either ADSP
or ADSC inputs. In Burst mode, subsequent burst addresses are
generated internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or interleave order
with the Linear Burst Order (LBO) input. The Burst function need not
be used. New addresses can be loaded on every cycle with no
degradation of chip performance.
Flow Through / Pipeline Reads
The function of the Data Output register can be controlled by the user
via the FT mode pin/bump (Pin 14 in the TQFP, bump 1F in the FP-
BGA). Holding the FT mode pin/bump low, places the RAM in Flow
through mode, causing output data to bypass the Data Output
Register. Holding FT high places the RAM in Pipelined Mode,
activating the rising edge triggered Data Output Register.
DCD Pipelined Reads
The GS820E32A is a DCD (Dual Cycle Deselect) pipelined
synchronous SRAM. SCD (Single Cycle Deselect) versions are also
available. DCD SRAMs pipeline disable commands to the same
degree as read commands. DCD RAMs hold the deselect command
for one full cycle and then begin turning off their outputs just after the
second rising edge of clock.
Byte Write and Global Write
Byte write operation is performed by using byte write enable (BW)
input combined with one or more individual byte write signals (Bx). In
addition, Global Write (GW) is available for writing all bytes at one
time, regardless of the Byte Write control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High) of
the ZZ signal, or by stopping the clock (CK). Memory data is retained
during Sleep mode.
Core and Interface Voltages
The GS820E32A operates on a 3.3V power supply and all inputs/
outputs are 3.3V and 2.5V compatible. Separate output power (V
DDQ
)
pins are used to de-couple output noise fromthe internal circuit.
-133
7.5ns
4ns
240mA
15ns
10ns
120mA
-117
8.5ns
4.5
210mA
15ns
11ns
120mA
-100
10ns
5ns
180mA
15ns
12ns
120mA
-66
tCycle
6.6ns
3.8ns
7.25ns
4ns
12.5ns
6ns
150mA
20ns
18ns
95mA
tCycle
t
KQ
10.5ns
9ns
15ns
9.7ns
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| GS820E32T-6I | 2M Synchronous Burst SRAM |
| GS820E32Q-100 | 2M Synchronous Burst SRAM |
| GS820E32Q-117 | 2M Synchronous Burst SRAM |
| GS820E32Q-133 | 2M Synchronous Burst SRAM |
| GS820E32Q-133I | 2M Synchronous Burst SRAM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| GS820E32AGT-133 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:64K x 32 2Mb Synchronous Burst SRAM |
| GS820E32AGT-133I | 制造商:GSI 制造商全稱:GSI Technology 功能描述:64K x 32 2Mb Synchronous Burst SRAM |
| GS820E32AGT-166 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:64K x 32 2Mb Synchronous Burst SRAM |
| GS820E32AGT-166I | 制造商:GSI 制造商全稱:GSI Technology 功能描述:64K x 32 2Mb Synchronous Burst SRAM |
| GS820E32AGT-180 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:64K x 32 2Mb Synchronous Burst SRAM |
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