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參數(shù)資料
| 型號： | GS832018T-200 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | DRAM |
| 英文描述： | 2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs |
| 中文描述： | 200萬× 18，100萬× 32，100萬× 36同步突發(fā)靜態(tài)存儲器分配36MB |
| 文件頁數(shù)： | 1/25頁 |
| 文件大小： | 669K |
| 代理商： | GS832018T-200 |
Preliminary
GS832018/32/36T-250/225/200/166/150/133
2M x 18, 1M x 32, 1M x 36
36Mb Sync Burst SRAMs
250 MHz
–
133 MHz
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
100-Pin TQFP
Commercial Temp
Industrial Temp
Rev: 1.02 10/2004
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
1/25
2003, GSI Technology
Features
FT pin for user-configurable flow through or pipeline
operation
Single Cycle Deselect (SCD) operation
2.5 V or 3.3 V +10%/
–
10% core power supply
2.5 V or 3.3 V I/O supply
LBO pin for Linear or Interleaved Burst mode
Internal input resistors on mode pins allow floating mode pins
Default to Interleaved Pipeline mode
Byte Write (BW) and/or Global Write (GW) operation
Internal self-timed write cycle
Automatic power-down for portable applications
JEDEC-standard 100-lead TQFP package
Pb-Free 100-lead TQFP package available
Functional Description
Applications
The GS832018/32/36T is a 37,748,736-bit high performance
synchronous SRAM with a 2-bit burst address counter.
Although of a type originally developed for Level 2 Cache
applications supporting high performance CPUs, the device
now finds application in synchronous SRAM applications,
ranging from DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode
pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the rising-
edge-triggered Data Output Register.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS832018/32/36T operates on a 2.5 V or 3.3 V power
supply. All input are 3.3 V and 2.5 V compatible. Separate
output power (V
DDQ
) pins are used to decouple output noise
from the internal circuits and are 3.3 V and 2.5 V compatible.
Parameter Synopsis
-250 -225 -200 -166 -150 -133 Unit
2.5
4.0
4.4
5.0
6.0
285
350
320
295
260
6.5
6.5
7.0
7.5
8.0
205
235
225
210
200
Pipeline
3-1-1-1
t
KQ
tCycle
Curr
(x18)
Curr
(x32/x36)
t
KQ
tCycle
Curr
(x18)
Curr
(x32/x36)
2.7
3.0
3.5
3.8
6.6
210
240
8.5
8.5
165
190
4.0
7.5
185
215
8.5
8.5
155
175
ns
ns
mA
mA
ns
ns
mA
mA
265
245
220
Flow
Through
2-1-1-1
7.0
7.5
8.0
195
185
175
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS832018T-200I | 2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs |
| GS832018T-225 | 2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs |
| GS832018T-225I | 2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs |
| GS832018T-250 | 2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs |
| GS832018T-250I | 2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS832018T-200I | 制造商:GSI 制造商全稱:GSI Technology 功能描述:2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs |
| GS832018T-200IV | 制造商:GSI 制造商全稱:GSI Technology 功能描述:2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs |
| GS832018T-200V | 制造商:GSI 制造商全稱:GSI Technology 功能描述:2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs |
| GS832018T-225 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs |
| GS832018T-225I | 制造商:GSI 制造商全稱:GSI Technology 功能描述:2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs |
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