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參數資料
| 型號： | GS8320Z18GT-250IT |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 36Mb Pipelined and Flow Through Synchronous NBT SRAM |
| 中文描述： | 流水線和流量分配36MB通過同步唑的SRAM |
| 文件頁數： | 1/24頁 |
| 文件大小： | 643K |
| 代理商： | GS8320Z18GT-250IT |
Preliminary
GS8320Z18/36T-250/225/200/166/150/133
36Mb Pipelined and Flow Through
Synchronous NBT SRAMs
250 MHz
–
133 MHz
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
100-Pin TQFP
Commercial Temp
Industrial Temp
Rev: 1.03 10/2004
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
1/24
2001, GSI Technology
Features
NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization; Fully pin-compatible with
both pipelined and flow through NtRAM, NoBL and
ZBT SRAMs
2.5 V or 3.3 V +10%/
–
10% core power supply
2.5 V or 3.3 V I/O supply
User-configurable Pipeline and Flow Through mode
LBO pin for Linear or Interleave Burst mode
Pin compatible with 2Mb, 4Mb, 8Mb, and 16Mb devices
Byte write operation (9-bit Bytes)
3 chip enable signals for easy depth expansion
ZZ Pin for automatic power-down
JEDEC-standard 100-lead TQFP package
Pb-Free 100-lead TQFP package available
Functional Description
The GS8320Z18/36T is a 36Mbit Synchronous Static SRAM.
GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other
pipelined read/double late write or flow through read/single
late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8320Z18/36T may be configured by the user to operate
in Pipeline or Flow Through mode. Operating as a pipelined
synchronous device, meaning that in addition to the rising edge
triggered registers that capture input signals, the device
incorporates a rising-edge-triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
The GS8320Z18/36T is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
standard 100-pin TQFP package.
Parameter Synopsis
-250 -225 -200 -166 -150 -133 Unit
2.5
4.0
4.4
5.0
6.0
285
350
320
295
260
6.5
6.5
7.0
7.5
8.0
205
235
225
210
200
Pipeline
3-1-1-1
t
KQ
tCycle
Curr
(x18)
Curr
(x32/x36)
t
KQ
tCycle
Curr
(x18)
Curr
(x32/x36)
2.7
3.0
3.5
3.8
6.6
210
240
8.5
8.5
165
190
4.0
7.5
185
215
8.5
8.5
155
175
ns
ns
mA
mA
ns
ns
mA
mA
265
245
220
Flow
Through
2-1-1-1
7.0
7.5
8.0
195
185
175
相關PDF資料 |
PDF描述 |
|---|---|
| GS8320Z18GT-250T | RESISTOR: CHIP, 1%, 1/10W, 5.11K |
| GS8320Z18T | RES,SM,5.62K,1/10W,1%,0805SMD |
| GS8320Z18T-133IT | 36Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8320Z18T-133T | 36Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8320Z18T-150IT | 36Mb Pipelined and Flow Through Synchronous NBT SRAM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| GS8320Z18GT-250IV | 制造商:GSI 制造商全稱:GSI Technology 功能描述:36Mb Pipelined and Flow Through Synchronous NBT SRAMs |
| GS8320Z18GT-250T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:36Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8320Z18GT-250V | 制造商:GSI 制造商全稱:GSI Technology 功能描述:36Mb Pipelined and Flow Through Synchronous NBT SRAMs |
| GS8320Z18T | 制造商:GSI 制造商全稱:GSI Technology 功能描述:36Mb Pipelined and Flow Through Synchronous NBT SRAMs |
| GS8320Z18T-133 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:36Mb Pipelined and Flow Through Synchronous NBT SRAM |
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