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參數資料
| 型號： | GS8321E18E-133 |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | DRAM |
| 英文描述： | 2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs |
| 中文描述： | 2M X 18 CACHE SRAM, 8.5 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1 MM PITCH, BUMP, FPBGA-165 |
| 文件頁數： | 1/34頁 |
| 文件大小： | 739K |
| 代理商： | GS8321E18E-133 |
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GS8321E18/32/36E-250/225/200/166/150/133
2M x 18, 1M x 32, 1M x 36
36Mb Sync Burst SRAMs
250 MHz
–
133 MHz
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
165-Bump FP-BGA
Commercial Temp
Industrial Temp
Rev: 1.03 4/2005
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
1/34
2003, GSI Technology
Features
FT pin for user-configurable flow through or pipeline
operation
Dual Cycle Deselect (DCD) operation
IEEE 1149.1 JTAG-compatible Boundary Scan
2.5 V or 3.3 V +10%/–10% core power supply
2.5 V or 3.3 V I/O supply
LBO pin for Linear or Interleaved Burst mode
Internal input resistors on mode pins allow floating mode pins
Default to Interleaved Pipeline mode
Byte Write (BW) and/or Global Write (GW) operation
Internal self-timed write cycle
Automatic power-down for portable applications
JEDEC-standard 165-bump FP-BGA package
Pb-Free 165-bump BGA package available
Functional Description
Applications
The GS8321E18/32/36E is a 37,748,736-bit high performance
synchronous SRAM with a 2-bit burst address counter.
Although of a type originally developed for Level 2 Cache
applications supporting high performance CPUs, the device
now finds application in synchronous SRAM applications,
ranging from DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV) and write control inputs (Bx,
BW, GW) are synchronous and are controlled by a positive-
edge-triggered clock input (CK). Output enable (G) and power
down control (ZZ) are asynchronous inputs. Burst cycles can
be initiated with either ADSP or ADSC inputs. In Burst mode,
subsequent burst addresses are generated internally and are
controlled by ADV. The burst address counter may be
configured to count in either linear or interleave order with the
Linear Burst Order (LBO) input. The Burst function need not
be used. New addresses can be loaded on every cycle with no
degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode
pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the rising-
edge-triggered Data Output Register.
DCD Pipelined Reads
The GS8321E18/32/36E is a DCD (Dual Cycle Deselect)
pipelined synchronous SRAM. SCD (Single Cycle Deselect)
versions are also available. DCD SRAMs pipeline disable
commands to the same degree as read commands. DCD RAMs
hold the deselect command for one full cycle and then begin
turning off their outputs just after the second rising edge of
clock.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS8321E18/32/36E operates on a 2.5 V or 3.3 V power
supply. All input are 3.3 V and 2.5 V compatible. Separate
output power (V
DDQ
) pins are used to decouple output noise
from the internal circuits and are 3.3 V and 2.5 V compatible.
Parameter Synopsis
-250 -225 -200 -166 -150 -133 Unit
2.5
4.0
4.4
5.0
6.0
285
330
290
255
235
5.5
5.5
6.0
6.5
7.0
205
235
225
210
200
Pipeline
3-1-1-1
t
KQ
tCycle
Curr
(x18)
Curr
(x32/x36)
t
KQ
tCycle
Curr
(x18)
Curr
(x32/x36)
2.7
3.0
3.5
3.8
6.6
190
220
7.5
7.5
165
190
4.0
7.5
165
195
8.5
8.5
155
175
ns
ns
mA
mA
ns
ns
mA
mA
250
215
200
Flow
Through
2-1-1-1
6.0
6.5
7.0
195
185
175
相關PDF資料 |
PDF描述 |
|---|---|
| GS8321E18E-133I | 2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs |
| GS8321E18E-150 | 2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs |
| GS8321E18E-150I | 2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs |
| GS8321E18E-166 | 2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs |
| GS8321E18E-166I | 2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs |
相關代理商/技術參數 |
參數描述 |
|---|---|
| GS8321E18E-133I | 制造商:GSI 制造商全稱:GSI Technology 功能描述:2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs |
| GS8321E18E-133IV | 制造商:GSI 制造商全稱:GSI Technology 功能描述:2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs |
| GS8321E18E-133V | 制造商:GSI 制造商全稱:GSI Technology 功能描述:2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs |
| GS8321E18E-150 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs |
| GS8321E18E-150I | 制造商:GSI 制造商全稱:GSI Technology 功能描述:2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs |
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