- 您現在的位置：買賣IC網 > PDF目錄385320 > GS8322V36GE-200 (GSI TECHNOLOGY) 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs PDF資料下載
參數資料
| 型號： | GS8322V36GE-200 |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | DRAM |
| 英文描述： | 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs |
| 中文描述： | 1M X 36 CACHE SRAM, 7.5 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1 MM PITCH, LEAD FREE, FPBGA-165 |
| 文件頁數： | 1/42頁 |
| 文件大?。?/td> | 1038K |
| 代理商： | GS8322V36GE-200 |
當前第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁
Preliminary
GS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)
2M x 18, 1M x 36, 512K x 72
36Mb S/DCD Sync Burst SRAMs
250 MHz
–
133 MHz
1.8 V V
DD
1.8 V I/O
119-, 165-, & 209-Pin BGA
Commercial Temp
Industrial Temp
Rev: 1.04 4/2005
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
1/42
2003, GSI Technology
Features
FT pin for user-configurable flow through or pipeline operation
Single/Dual Cycle Deselect selectable
IEEE 1149.1 JTAG-compatible Boundary Scan
ZQ mode pin for user-selectable high/low output drive
1.8 V +10%/–10% core power supply
1.8 V +10%/–10% core power supply
1.8 V I/O supply
LBO pin for Linear or Interleaved Burst mode
Internal input resistors on mode pins allow floating mode pins
Default to SCD x18/x36 Interleaved Pipeline mode
Byte Write (BW) and/or Global Write (GW) operation
Internal self-timed write cycle
Automatic power-down for portable applications
JEDEC-standard 119-, 165-, and 209-bump BGA package
Pb-Free packages available
Functional Description
Applications
The GS8322V18/36/72 is a
37,748,736
-bit high performance
synchronous SRAM with a 2-bit burst address counter. Although
of a type originally developed for Level 2 Cache applications
supporting high performance CPUs, the device now finds
application in synchronous SRAM applications, ranging from
DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,
GW) are synchronous and are controlled by a positive-edge-
triggered clock input (CK). Output enable (G) and power down
control (ZZ) are asynchronous inputs. Burst cycles can be initiated
with either ADSP or ADSC inputs. In Burst mode, subsequent
burst addresses are generated internally and are controlled by
ADV. The burst address counter may be configured to count in
either linear or interleave order with the Linear Burst Order (LBO)
input. The Burst function need not be used. New addresses can be
loaded on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by the
user via the FT mode . Holding the FT mode pin low places the
RAM in Flow Through mode, causing output data to bypass the
Data Output Register. Holding FT high places the RAM in
Pipeline mode, activating the rising-edge-triggered Data Output
Register.
SCD and DCD Pipelined Reads
The GS8322V18/36/72 is a SCD (Single Cycle Deselect) and
DCD (Dual Cycle Deselect) pipelined synchronous SRAM. DCD
SRAMs pipeline disable commands to the same degree as read
commands. SCD SRAMs pipeline deselect commands one stage
less than read commands. SCD RAMs begin turning off their
outputs immediately after the deselect command has been
captured in the input registers. DCD RAMs hold the deselect
command for one full cycle and then begin turning off their
outputs just after the second rising edge of clock. The user may
configure this SRAM for either mode of operation using the SCD
mode input.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write control
inputs.
FLXDrive
The ZQ pin allows selection between high drive strength (ZQ low)
for multi-drop bus applications and normal drive strength (ZQ
floating or high) point-to-point applications. See the Output Driver
Characteristics chart for details.
Parameter Synopsis
-250
-225
t
KQ
(x18/x36)
t
KQ
(x72)
tCycle
Curr (x18)
Curr (x36)
Curr (x72)
440
t
KQ
tCycle
6.5
Curr (x18)
Curr (x36)
Curr (x72)
315
-200
3.0
3.0
5.0
-166
3.5
3.5
6.0
-150 -133 Unit
3.8
3.8
6.7
7.5
Pipeline
3-1-1-1
2.5
3.0
4.0
2.7
3.0
4.4
4.0
4.0
ns
ns
ns
285
350
265
320
410
7.0
7.0
195
225
295
245
295
370
7.5
7.5
185
210
265
220
260
320
8.0
8.0
175
200
255
210
240
300
8.5
8.5
165
190
240
185
215
265
8.5
8.5
155
175
230
mA
mA
mA
ns
ns
mA
mA
mA
Flow
Through
2-1-1-1
6.5
205
235
相關PDF資料 |
PDF描述 |
|---|---|
| GS8322V36GE-200I | 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs |
| GS8322V36GE-225 | 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs |
| GS8322V36GE-225I | 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs |
| GS8322V36GE-250 | 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs |
| GS8322V36GE-250I | 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs |
相關代理商/技術參數 |
參數描述 |
|---|---|
| GS8322V72C-133 | 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 1.8V 36MBIT 512KX72 8.5NS/4NS 209FBGA - Trays |
| GS8322V72C-133I | 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 1.8V 36MBIT 512KX72 8.5NS/4NS 209FBGA - Trays |
| GS8322V72C-150 | 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 1.8V 36MBIT 512KX72 8.5NS/3.8NS 209FBGA - Trays |
| GS8322V72C-150I | 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 1.8V 36MBIT 512KX72 8.5NS/3.8NS 209FBGA - Trays |
| GS8322V72C-166 | 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 1.8V 36MBIT 512KX72 8NS/3.5NS 209FBGA - Trays |
發布緊急采購，3分鐘左右您將得到回復。