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參數資料
型號: GS8322V72GC-200
廠商: GSI TECHNOLOGY
元件分類: DRAM
英文描述: 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs
中文描述: 512K X 72 CACHE SRAM, 7.5 ns, PBGA209
封裝: 14 X 22 MM, 1 MM PITCH, LEAD FREE, BGA-209
文件頁數: 28/42頁
文件大小: 1038K
代理商: GS8322V72GC-200
Instruction Register
ID Code Register
·
31 30 29
Boundary Scan Register
0
1
2
0
· · ·
1
2
0
Bypass Register
TDI
TDO
TMS
TCK
Test Access Port (TAP) Controller
1
·
1
0
·
·
·
·
·
·
·
·
·
Control Signals
·
Preliminary
GS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04 4/2005
28/42
2003, GSI Technology
JTAG TAP Block Diagram
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
ID Register Contents TBD for this part.
相關PDF資料
PDF描述
GS8322V72GC-200I 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs
GS8322V72GC-225 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs
GS8322V72GC-225I 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs
GS8322V72GC-250 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs
GS8322V18B 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs
相關代理商/技術參數
參數描述
GS8322V72GC-250 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 1.8V 36MBIT 512KX72 6.5NS/3NS 209FBGA - Trays
GS8322Z18AB-200I 制造商:GSI Technology 功能描述:119 BGA - Bulk
GS8322Z18AB-200IV 制造商:GSI Technology 功能描述:165 BGA - Bulk
GS8322Z18AB-200V 制造商:GSI Technology 功能描述:165 BGA - Bulk
GS8322Z18AB-250 制造商:GSI Technology 功能描述:119 BGA - Bulk
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