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| 型號： | GS8322ZV18B-200I |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | DRAM |
| 英文描述： | 36Mb Pipelined and Flow Through Synchronous NBT SRAM |
| 中文描述： | 2M X 18 ZBT SRAM, 7.5 ns, PBGA119 |
| 封裝： | 14 X 22 MM, 1.27 PITCH, FPBGA-119 |
| 文件頁數(shù)： | 22/39頁 |
| 文件大小： | 975K |
| 代理商： | GS8322ZV18B-200I |
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AC Electrical Characteristics
Parameter
Symbol
-250
-225
-200
-166
-150
-133
Unit
Min
4.0
Max
—
Min
4.4
Max
—
Min
5.0
Max
—
Min
6.0
Max
—
Min
6.7
Max
—
Min
7.5
Max
—
Pipeline
Clock Cycle Time
Clock to Output Valid
(x18/x36)
Clock to Output Valid
(x72)
Clock to Output Invalid
tKC
ns
tKQ
—
2.5
—
2.7
—
3.0
—
3.5
—
3.8
—
4.0
ns
tKQ
—
3.0
—
3.0
—
3.0
—
3.5
—
3.8
—
4.0
ns
tKQX
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
ns
Clock to Output in Low-Z
tLZ
1
tS
tKC
tKQ
tKQX
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
ns
Setup time
Clock Cycle Time
Clock to Output Valid
Clock to Output Invalid
1.2
6.5
—
3.0
—
—
6.5
—
1.3
7.0
—
3.0
—
—
7.0
—
1.4
7.5
—
3.0
—
—
7.5
—
1.5
8.0
—
3.0
—
—
8.0
—
1.5
8.5
—
3.0
—
—
8.5
—
1.5
8.5
—
3.0
—
—
8.5
—
ns
ns
ns
ns
Flow
Through
Clock to Output in Low-Z
tLZ
1
tS
tH
tKH
tKL
3.0
—
3.0
—
3.0
—
3.0
—
3.0
—
3.0
—
ns
Setup time
Hold time
Clock HIGH Time
Clock LOW Time
Clock to Output in
High-Z
(x18/x36)
Clock to Output in
High-Z
(x72)
G to Output Valid
(x18/x36)
G to Output Valid
(x72)
1.5
0.5
1.3
1.5
—
—
—
—
1.5
0.5
1.3
1.5
—
—
—
—
1.5
0.5
1.3
1.5
—
—
—
—
1.5
0.5
1.3
1.5
—
—
—
—
1.5
0.5
1.5
1.7
—
—
—
—
1.5
0.5
1.7
2
—
—
—
—
ns
ns
ns
ns
tHZ
1
1.5
2.5
1.5
2.7
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.0
ns
tHZ
1
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.0
ns
tOE
—
2.5
—
2.7
—
3.0
—
3.5
—
3.8
—
4.0
ns
tOE
—
3.0
—
3.0
—
3.0
—
3.5
—
3.8
—
4.0
ns
G to output in Low-Z
tOLZ
1
0
—
0
—
0
—
0
—
0
—
0
—
ns
G to output in High-Z
(x18/x36)
G to output in High-Z
(x72)
tOHZ
1
—
2.5
—
2.7
—
3.0
—
3.0
—
3.0
—
3.0
ns
tOHZ
1
—
3.0
—
3.0
—
3.0
—
3.0
—
3.0
—
3.0
ns
ZZ setup time
tZZS
2
5
—
5
—
5
—
5
—
5
—
5
—
ns
ZZ hold time
tZZH
2
tZZR
1
—
1
—
1
—
1
—
1
—
1
—
ns
ZZ recovery
20
—
20
—
20
—
20
—
20
—
20
—
ns
GS8322ZV18(B/E)/GS8322ZV36(B/E)/GS8322ZV72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03a 2/2006
22/39
2002, GSI Technology
Notes:
1.
2.
These parameters are sampled and are not 100% tested.
ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
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| GS8322ZV18B-225 | 36Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8322ZV18B-225I | 36Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8322ZV18B-250 | 36Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8322ZV18B-250I | 36Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8322ZV18E-133 | 36Mb Pipelined and Flow Through Synchronous NBT SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS8322ZV72C-133 | 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 1.8V 36MBIT 512KX72 8.5NS/4NS 209FBGA - Trays |
| GS8322ZV72C-150 | 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 1.8V 36MBIT 512KX72 8.5NS/3.8NS 209FBGA - Trays |
| GS8322ZV72C-166 | 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 1.8V 36MBIT 512KX72 8NS/3.5NS 209FBGA - Trays |
| GS8324Z36B-133 | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 2.5V/3.3V 36MBIT 1MX36 10NS/4NS 119FBGA - Trays |
| GS8324Z36B-200I | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 2.5V/3.3V 36MBIT 1MX36 7.5NS/3NS 119FBGA - Trays |
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