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參數資料
| 型號： | GS832418B-166I |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | DRAM |
| 英文描述： | 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs |
| 中文描述： | 2M X 18 CACHE SRAM, 8.5 ns, PBGA119 |
| 封裝： | 14 X 22 MM, 1.27 MM PITCH, BGA-119 |
| 文件頁數： | 16/46頁 |
| 文件大小： | 1149K |
| 代理商： | GS832418B-166I |
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Rev: 1.00 10/2001
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
16/46
2001, Giga Semiconductor, Inc.
Preliminary
GS832418(B/C)/GS832436(B/C)/GS832472(C)
Synchronous Truth Table (x18 209-Bump BGA and x36/x18 119-Bump BGA)
Operation
Address Used
State
Diagram
Key
5
X
R
R
W
CR
CR
CW
CW
E
1
ADSP
ADSC
ADV
W
3
DQ
4
Deselect Cycle, Power Down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Notes:
1.
X = Don’t Care, H = High, L = Low
2.
W = T (True) and F (False) is defined in the Byte Write Truth Table preceding
3.
G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown
as “Q” in the Truth Table above).
4.
All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish
basic synchronous or synchronous burst operations and may be avoided for simplicity.
5.
Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See
BOLD
items above.
6.
Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See
ITALIC
items above.
None
External
External
External
Next
Next
Next
Next
Current
Current
Current
Current
H
L
L
L
X
H
X
H
X
H
X
H
X
L
H
H
H
X
H
X
H
X
H
X
L
X
L
L
H
H
H
H
H
H
H
H
X
X
X
X
L
L
L
L
H
H
H
H
X
X
F
T
F
F
T
T
F
F
T
T
High-Z
Q
Q
D
Q
Q
D
D
Q
Q
D
D
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