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參數(shù)資料
| 型號： | GS8330DW36-250 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | DC/DC變換器 |
| 英文描述： | 1 watt dc-dc converters |
| 中文描述： | 1瓦的DC - DC轉(zhuǎn)換器 |
| 文件頁數(shù)： | 1/30頁 |
| 文件大小： | 583K |
| 代理商： | GS8330DW36-250 |
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Rev: 1.00 6/2003
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
1/30
2003, GSI Technology, Inc.
Preliminary
GS8330DW36/72C-250/200
36Mb
Σ
1x1Dp CMOS I/O
Double Late Write SigmaRAM
200 MHz–250 MHz
1.8 V V
DD
1.8 V I/O
209-Bump BGA
Commercial Temp
Industrial Temp
Features
Double Late Write mode, Pipelined Read mode
JEDEC-standard SigmaRAM
pinout and package
1.8 V +150/–100 mV core power supply
1.8 V CMOS Interface
ZQ controlled user-selectable output drive strength
Dual Cycle Deselect
Burst Read and Write option
Fully coherent read and write pipelines
Echo Clock outputs track data output drivers
Byte write operation (9-bit bytes)
2 user-programmable chip enable inputs
IEEE 1149.1 JTAG-compliant Serial Boundary Scan
209-bump, 14 mm x 22 mm, 1 mm bump pitch BGA package
Pin-compatible with future 72Mb and 144Mb devices
SigmaRAM Family Overview
GS8330
DW
36/72 SigmaRAMs are built in compliance with
the SigmaRAM pinout standard for synchronous SRAMs.
They are 37,748,736-bit (36Mb) SRAMs. This family of wide,
very low voltage CMOS I/O SRAMs is designed to operate at
the speeds needed to implement economical high performance
networking systems.
Σ
RAMs are offered in a number of configurations including
Late Write, Double Late Write, and Double Data Rate (DDR).
The logical differences between the protocols employed by
these RAMs mainly involve various approaches to write
cueing and data transfer rates. The
Σ
RAM
family standard
allows a user to implement the interface protocol best suited to
the task at hand.
Functional Description
Because SigmaRAMs are synchronous devices, address data
inputs and read/write control inputs are captured on the rising
edge of the input clock. Write cycles are internally self-timed
and initiated by the rising edge of the clock input. This feature
eliminates complex off-chip write pulse generation required by
asynchronous SRAMs and simplifies input signal timing.
Σ
RAMs support pipelined reads utilizing a rising-edge-
triggered output register. They also utilize a Dual Cycle
Deselect (DCD) output deselect protocol.
Σ
RAMs are implemented with high performance CMOS
technology and are packaged in a 209-bump BGA.
Key Fast Bin Specs
Symbol
-250
Cycle Time
tKHKH
4.0 ns
Access Time
tKHQV
2.1 ns
209-Bump, 14 mm x 22 mm BGA
1 mm Bump Pitch, 11 x 19 Bump Array
Bottom View
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