- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383049 > GS84036AB-166 (Electronic Theatre Controls, Inc.) 256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs PDF資料下載
參數(shù)資料
| 型號： | GS84036AB-166 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs |
| 中文描述： | 256 × 18，128K的× 32，128K的× 36 4Mb的同步突發(fā)靜態(tài)存儲器 |
| 文件頁數(shù)： | 1/31頁 |
| 文件大小： | 911K |
| 代理商： | GS84036AB-166 |
當(dāng)前第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁
Rev: 1.12 7/2002
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
1/31
1999, Giga Semiconductor, Inc.
Preliminary
GS84018/32/36AT/B-180/166/150/100
256K x 18, 128K x 32, 128K x 36
4Mb Sync Burst SRAMs
180 MHz–100 MHz
3.3 V V
DD
3.3 V and 2.5 V I/O
TQFP, BGA
Commercial Temp
Industrial Temp
Features
FT pin for user-configurable flow through or pipelined
operation
Single Cycle Deselect (SCD) operation
3.3 V +10%/–5% core power supply
2.5 V or 3.3 V I/O supply
LBO pin for Linear or Interleaved Burst mode
Internal input resistors on mode pins allow floating mode pins
Default to Interleaved Pipelined mode
Byte Write (BW) and/or Global Write (GW) operation
Common data inputs and data outputs
Clock control, registered, address, data, and control
Internal self-timed write cycle
Automatic power-down for portable applications
JEDEC standard 100-lead TQFP or 119-Bump BGA package
–180
tCycle
t
KQ
I
DD
185 mA
Flow
Through
2-1-1-1
I
DD
115 mA
Functional Description
Applications
The GS84018/32/36A is a 4,718,592-bit (4,194,304-bit for
x32 version) high performance synchronous SRAM with a 2-
bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPUs, the device now finds application in
synchronous SRAM applications ranging from DSP main store
to networking chip set support. The GS84018/32/36A is
available in a JEDEC standard 100-lead TQFP or 119-Bump
BGA package.
Controls
Addresses, data I/Os, chip enables (E
1
, E
2
, E
3
), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin/bump (pin 14 in the TQFP and
bump 5R in the BGA). Holding the FT mode pin/bump low
places the RAM in Flow Through mode, causing output data to
bypass the Data Output Register. Holding FT high places the
RAM in Pipelined mode, activating the rising-edge-triggered
Data Output Register.
SCD Pipelined Reads
The GS84018/32/36A is an SCD (Single Cycle Deselect)
pipelined synchronous SRAM. DCD (Dual Cycle Deselect)
versions are also available. SCD SRAMs pipeline deselect
commands one stage less than read commands. SCD RAMs
begin turning off their outputs immediately after the deselect
command has been captured in the input registers.
Byte Write and Global Write
Byte write operation is performed by using byte write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS84018/32/36A operates on a 3.3 V power supply and
all inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate
output power (V
DDQ
) pins are used to de-couple output noise
from the internal circuit.
–166
6.0 ns
3.5 ns
170 mA
8.5 ns
10 ns
105 mA
–150
6.6 ns
3.8 ns
155 mA
10 ns
12 ns
100 mA
–100
10 ns
4.5 ns
105 mA
12 ns
15 ns
80 mA
Pipeline
3-1-1-1
5.5 ns
3.0 ns
t
KQ
tCycle
8 ns
9.1 ns
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS84036AB-166I | 256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs |
| GS84032AT-166I | 256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs |
| GS84032AT-180 | 256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs |
| GS84036AT-150 | XC17S15AVOG8C |
| GS84036AT-150I | 256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS84036AB-166I | 制造商:GSI Technology 功能描述:SRAM SYNC SGL 3.3V 4.5MBIT 128KX36 8.5NS/3.5NS 119FBGA - Trays |
| GS84036AB-180 | 制造商:GSI Technology 功能描述:SRAM SYNC SGL 3.3V 4.5MBIT 128KX36 8NS/3NS 119FBGA - Trays |
| GS84036AB-180I | 制造商:GSI Technology 功能描述:SRAM SYNC SGL 3.3V 4.5MBIT 128KX36 8NS/3NS 119FBGA - Trays |
| GS84036AGB-100 | 制造商:GSI Technology 功能描述:SRAM SYNC SGL 3.3V 4.5MBIT 128KX36 12NS/4.5NS 119FBGA - Trays |
| GS84036AGB-100I | 制造商:GSI Technology 功能描述:SRAM SYNC SGL 3.3V 4.5MBIT 128KX36 12NS/4.5NS 119FBGA - Trays |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。