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參數資料
| 型號： | GS864018T-200V |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | DRAM |
| 英文描述： | 4M x 18, 2M x 32, 2M x 36 72Mb Sync Burst SRAMs |
| 中文描述： | 4M X 18 CACHE SRAM, 7.5 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數： | 7/23頁 |
| 文件大小： | 603K |
| 代理商： | GS864018T-200V |
Mode Pin Functions
Mode Name
Pin Name
State
L
H
L
H or NC
L or NC
Function
Linear Burst
Interleaved Burst
Flow Through
Pipeline
Active
Standby, I
DD
= I
SB
Burst Order Control
LBO
Output Register Control
FT
Power Down Control
ZZ
H
GS864018/32/36T-xxxV
Preliminary
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.01 6/2006
7/23
2004, GSI Technology
Note:
There is a pull-up device on the FT pin and a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in
the default states as specified in the above table.
Note:
The burst counter wraps to initial state on the 5th clock.
Note:
The burst counter wraps to initial state on the 5th clock.
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
00
11
10
3rd address
10
11
00
01
4th address
11
10
01
00
Burst Counter Sequences
BPR 1999.05.18
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相關代理商/技術參數 |
參數描述 |
|---|---|
| GS864018T-250 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:4M x 18, 2M x 32, 2M x 36 72Mb Sync Burst SRAMs |
| GS864018T-250I | 制造商:GSI 制造商全稱:GSI Technology 功能描述:4M x 18, 2M x 32, 2M x 36 72Mb Sync Burst SRAMs |
| GS864018T-250IV | 制造商:GSI 制造商全稱:GSI Technology 功能描述:4M x 18, 2M x 32, 2M x 36 72Mb Sync Burst SRAMs |
| GS864018T-250V | 制造商:GSI 制造商全稱:GSI Technology 功能描述:4M x 18, 2M x 32, 2M x 36 72Mb Sync Burst SRAMs |
| GS864018T-300 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:4M x 18, 2M x 32, 2M x 36 72Mb Sync Burst SRAMs |
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