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參數資料
| 型號： | GS8640E36T-250V |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | DRAM |
| 英文描述： | 4M x 18, 2M x 32, 2M x 36 72Mb Sync Burst SRAMs |
| 中文描述： | 2M X 36 CACHE SRAM, 6.5 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數： | 8/23頁 |
| 文件大小： | 601K |
| 代理商： | GS8640E36T-250V |
GS8640E18/32/36T-xxxV
Preliminary
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.01 6/2006
8/23
2004, GSI Technology
Byte Write Truth Table
Function
GW
BW
B
A
B
B
B
C
B
D
Notes
Read
H
H
X
X
X
X
1
Read
H
L
H
H
H
H
1
Write byte a
H
L
L
H
H
H
2, 3
Write byte b
H
L
H
L
H
H
2, 3
Write byte c
H
L
H
H
L
H
2, 3, 4
Write byte d
H
L
H
H
H
L
2, 3, 4
Write all bytes
H
L
L
L
L
L
2, 3, 4
Write all bytes
Notes:
1.
All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
2.
Byte Write Enable inputs B
A
, B
B
, B
C
and/or B
D
may be used in any combination with BW to write single or multiple bytes.
3.
All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
4.
Bytes “
C
” and “
D
” are only available on the x32 and x36 versions.
L
X
X
X
X
X
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| GS8640E18GT-167IV | 4M x 18, 2M x 32, 2M x 36 72Mb Sync Burst SRAMs |
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| GS8640E18GT-200IV | 4M x 18, 2M x 32, 2M x 36 72Mb Sync Burst SRAMs |
| GS8640E18GT-200V | 4M x 18, 2M x 32, 2M x 36 72Mb Sync Burst SRAMs |
| GS8640E18GT-250IV | 4M x 18, 2M x 32, 2M x 36 72Mb Sync Burst SRAMs |
相關代理商/技術參數 |
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| GS8640EV18T-200 | 制造商:GSI Technology 功能描述:4M X 18 (72 MEG) SYNCH BURST DCD - Trays |
| GS8640EV18T-300 | 制造商:GSI Technology 功能描述:4M X 18 (72 MEG) SYNCH BURST DCD - Trays |
| GS8640EV18T-300I | 制造商:GSI Technology 功能描述:4M X 18 (72 MEG) SYNCH BURST DCD - Trays |
| GS8640FZ18GT-5.5 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 3.3V 72MBIT 4MX18 5.5NS 100TQFP - Trays |
| GS8640FZ18GT-6.5 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 3.3V 72MBIT 4MX18 6.5NS 100TQFP - Trays |
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