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參數資料
| 型號： | GS8640Z18GT-250V |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | DRAM |
| 英文描述： | 72Mb Pipelined and Flow Through Synchronous NBT SRAM |
| 中文描述： | 4M X 18 ZBT SRAM, 6.5 ns, PQFP100 |
| 封裝： | ROHS COMPLIANT, TQFP-100 |
| 文件頁數： | 1/22頁 |
| 文件大小： | 600K |
| 代理商： | GS8640Z18GT-250V |
Preliminary
GS8640Z18/36T-xxxV
72Mb Pipelined and Flow Through
Synchronous NBT SRAM
250 MHz
–
167 MHz
1.8 V or 2.5 V V
DD
1.8 V or 2.5 V I/O
100-Pin TQFP
Commercial Temp
Industrial Temp
Rev: 1.01 6/2006
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
1/22
2004, GSI Technology
Features
NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization; Fully pin-compatible with
both pipelined and flow through NtRAM, NoBL and
ZBT SRAMs
1.8 V or 2.5 V core power supply
1.8 V or 2.5 V I/O supply
User-configurable Pipeline and Flow Through mode
LBO pin for Linear or Interleave Burst mode
Pin compatible with 4Mb, 9Mb, 18Mb and 36Mb devices
Byte write operation (9-bit Bytes)
3 chip enable signals for easy depth expansion
ZZ Pin for automatic power-down
JEDEC-standard 100-lead TQFP package
RoHS-compliant 100-lead TQFP package available
Functional Description
The GS8640Z18/36T-xxxV is a 72Mbit Synchronous Static
SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or
other pipelined read/double late write or flow through read/
single late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8640Z18/36T-xxxV may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, meaning that in addition to the
rising edge triggered registers that capture input signals, the
device incorporates a rising-edge-triggered output register. For
read cycles, pipelined SRAM output data is temporarily stored
by the edge triggered output register during the access cycle
and then released to the output drivers at the next rising edge of
clock.
The GS8640Z18/36T-xxxV is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
standard 100-pin TQFP package.
Parameter Synopsis
-250
3.0
4.0
340
410
6.5
6.5
245
280
-200
3.0
5.0
290
350
7.5
7.5
220
250
-167
3.5
6.0
260
305
8.0
8.0
210
240
Unit
ns
ns
mA
mA
ns
ns
mA
mA
Pipeline
3-1-1-1
t
KQ
tCycle
Curr
(x18)
Curr
(x32/x36)
t
KQ
tCycle
Curr
(x18)
Curr
(x32/x36)
Flow Through
2-1-1-1
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