- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385329 > GS864218B-V (GSI TECHNOLOGY) 4M x 18, 2M x 36, 1M x 72 72Mb S/DCD Sync Burst SRAMs PDF資料下載
參數(shù)資料
| 型號(hào)： | GS864218B-V |
| 廠商： | GSI TECHNOLOGY |
| 英文描述： | 4M x 18, 2M x 36, 1M x 72 72Mb S/DCD Sync Burst SRAMs |
| 中文描述： | 4米× 18，200萬× 36，100萬× 72 72Mb的S /雙氰胺同步突發(fā)靜態(tài)存儲(chǔ)器 |
| 文件頁(yè)數(shù)： | 23/35頁(yè) |
| 文件大小： | 934K |
| 代理商： | GS864218B-V |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)當(dāng)前第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)
Preliminary
GS864218/36/72(B/C)-xxxV
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03 6/2006
23/35
2004, GSI Technology
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after ZZ recovery time.
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I
SB
2. The duration of
Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, I
SB
2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands
may be applied while the SRAM is recovering from Sleep mode.
Sleep Mode Timing
tZZR
tZZH
tZZS
Hold
Setup
tKL
tKH
tKC
CK
ADSP
ADSC
ZZ
Application Tips
Single and Dual Cycle Deselect
SCD devices (like this one) force the use of “dummy read cycles” (read cycles that are launched normally, but that are ended with
the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance, but their use usually
assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste
bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at
bank address boundary crossings), but greater care must be exercised to avoid excessive bus contention.
JTAG Port Operation
Overview
The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan
interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V
DD
. The JTAG output
drivers are powered by V
DDQ
.
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG
Port unused, TCK, TDI, and TMS may be left floating or tied to either V
DD
or V
SS
. TDO should be left unconnected.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS864218GB-167IV | 4M x 18, 2M x 36, 1M x 72 72Mb S/DCD Sync Burst SRAMs |
| GS864218GB-167V | 4M x 18, 2M x 36, 1M x 72 72Mb S/DCD Sync Burst SRAMs |
| GS864218GB-200IV | 4M x 18, 2M x 36, 1M x 72 72Mb S/DCD Sync Burst SRAMs |
| GS864218GB-200V | 4M x 18, 2M x 36, 1M x 72 72Mb S/DCD Sync Burst SRAMs |
| GS864218GB-250IV | 4M x 18, 2M x 36, 1M x 72 72Mb S/DCD Sync Burst SRAMs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS864218GB-167IV | 制造商:GSI 制造商全稱:GSI Technology 功能描述:4M x 18, 2M x 36, 1M x 72 72Mb S/DCD Sync Burst SRAMs |
| GS864218GB-167V | 制造商:GSI 制造商全稱:GSI Technology 功能描述:4M x 18, 2M x 36, 1M x 72 72Mb S/DCD Sync Burst SRAMs |
| GS864218GB-200 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V/3.3V 72MBIT 4MX18 7.5NS/3NS 119FBGA - Trays |
| GS864218GB-200I | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V/3.3V 72MBIT 4MX18 7.5NS/3NS 119FBGA - Trays |
| GS864218GB-200IV | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V/2.5V 72MBIT 4MX18 7.5NS/3NS 119FBGA - Trays |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。