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參數資料

First Write

First Read

Burst Write

Burst Read

Deselect

Notes:

The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.

The upper portion of the diagram assumes active use of only the Enable (E1) and Write (B

, B

, BW, and GW) control inputs, and

that ADSP is tied high and ADSC is tied low.

The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs and

assumes ADSP is tied high and ADV is tied low.

Preliminary

GS864418/36E-xxxV

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Rev: 1.05 6/2006

9/32

2003, GSI Technology

Simplified State Diagram

相關代理商/技術參數	參數描述
GS864418E-166IV	制造商:GSI 制造商全稱:GSI Technology 功能描述:4M x 18, 2M x 36 72Mb S/DCD Sync Burst SRAMs
GS864418E-166V	制造商:GSI 制造商全稱:GSI Technology 功能描述:4M x 18, 2M x 36 72Mb S/DCD Sync Burst SRAMs
GS864418E-200	制造商:GSI 制造商全稱:GSI Technology 功能描述:4M x 18, 2M x 36 72Mb S/DCD Sync Burst SRAMs
GS864418E-200I	制造商:GSI 制造商全稱:GSI Technology 功能描述:4M x 18, 2M x 36, 1M x 72 72Mb S/DCD Sync Burst SRAMs
GS864418E-200IV	制造商:GSI 制造商全稱:GSI Technology 功能描述:4M x 18, 2M x 36 72Mb S/DCD Sync Burst SRAMs

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