欧美成人免费电影,国产欧美一区二区三区精品酒店,精品国产a毛片,色网在线免费观看

參數資料
型號: GS8644ZV36B-225
廠商: GSI TECHNOLOGY
元件分類: DRAM
英文描述: 72Mb Pipelined and Flow Through Synchronous NBT SRAM
中文描述: 2M X 36 ZBT SRAM, 6.5 ns, PBGA119
封裝: 14 X 22 MM, 1.27 MM PITCH, FBGA-119
文件頁數: 12/37頁
文件大?。?/td> 776K
代理商: GS8644ZV36B-225
Product Preview
GS8644ZV18(B/E)/GS8644ZV36(B/E)/GS8644ZV72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03 11/2004
12/37
2003, GSI Technology
Synchronous Truth Table
Operation
Type
Address
CK CKE ADV W Bx E
1
E
2
E
3
G ZZ
DQ
Notes
Read Cycle, Begin Burst
R
External
L-H
L
L
H
X
L
H
L
L
L
Q
Read Cycle, Continue Burst
B
Next
L-H
L
H
X
X
X
X
X
L
L
Q
1,10
NOP/Read, Begin Burst
R
External
L-H
L
L
H
X
L
H
L
H
L
High-Z
2
Dummy Read, Continue Burst
B
Next
L-H
L
H
X
X
X
X
X
H
L
High-Z
1,2,10
Write Cycle, Begin Burst
W
External
L-H
L
L
L
L
L
H
L
X
L
D
3
Write Cycle, Continue Burst
B
Next
L-H
L
H
X
L
X
X
X
X
L
D
1,3,10
Write Abort, Continue Burst
B
Next
L-H
L
H
X
H
X
X
X
X
L
High-Z 1,2,3,10
Deselect Cycle, Power Down
D
None
L-H
L
L
X
X
H
X
X
X
L
High-Z
Deselect Cycle, Power Down
D
None
L-H
L
L
X
X
X
X
H
X
L
High-Z
Deselect Cycle, Power Down
D
None
L-H
L
L
X
X
X
L
X
X
L
High-Z
Deselect Cycle
D
None
L-H
L
L
L
H
L
H
L
X
L
High-Z
1
Deselect Cycle, Continue
D
None
L-H
L
H
X
X
X
X
X
X
L
High-Z
1
Sleep Mode
None
X
X
X
X
X
X
X
X
X
H
High-Z
Clock Edge Ignore, Stall
Current
L-H
H
X
X
X
X
X
X
X
L
-
4
Notes:
1.
Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Dese-
lect cycle is executed first.
Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W
pin is sampled low but no Byte Write pins are active so no write operation is performed.
G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during
write cycles.
If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus
will remain in High Z.
X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write
signals are Low
All inputs, except G and ZZ must meet setup and hold times of rising clock edge.
Wait states can be inserted by setting CKE high.
This device contains circuitry that ensures all outputs are in High Z during power-up.
A 2-bit burst counter is incorporated.
10. The address counter is incriminated for all Burst continue cycles.
2.
3.
4.
5.
6.
7.
8.
9.
相關PDF資料
PDF描述
GS8644ZV36B-225I 72Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8644ZV36B-250 72Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8644ZV36B-250I 72Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8644ZV36E-133 72Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8644ZV36E-133I 72Mb Pipelined and Flow Through Synchronous NBT SRAM
相關代理商/技術參數
參數描述
GS8644ZV36B-225I 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8644ZV36B-250 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8644ZV36B-250I 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8644ZV36E-133 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 72MBIT 2MX36 8.5NS/3.5NS 165FBGA - Trays
GS8644ZV36E-133I 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 72MBIT 2MX36 8.5NS/3.5NS 165FBGA - Trays
主站蜘蛛池模板: 明光市| 石棉县| 改则县| 宣汉县| 旌德县| 南康市| 大埔县| 宽城| 外汇| 莒南县| 高州市| 休宁县| 秀山| 甘肃省| 巴塘县| 关岭| 宾阳县| 民权县| 哈密市| 井研县| 昭平县| 大连市| 高淳县| 洪洞县| 玉屏| 湖北省| 古浪县| 昌黎县| 宁陕县| 楚雄市| 兴安盟| 当涂县| 梅州市| 镇坪县| 滕州市| 岗巴县| 南溪县| 田东县| 新安县| 武威市| 长宁县|