欧美成人免费电影,国产欧美一区二区三区精品酒店,精品国产a毛片,色网在线免费观看

參數資料
型號: GS8644ZV36E-200
廠商: GSI TECHNOLOGY
元件分類: DRAM
英文描述: 72Mb Pipelined and Flow Through Synchronous NBT SRAM
中文描述: 2M X 36 ZBT SRAM, 6.5 ns, PBGA165
封裝: 15 X 17 MM, 1 MM PITCH, FBGA-165
文件頁數: 27/37頁
文件大小: 776K
代理商: GS8644ZV36E-200
Product Preview
GS8644ZV18(B/E)/GS8644ZV36(B/E)/GS8644ZV72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03 11/2004
27/37
2003, GSI Technology
JTAG Tap Controller State Diagram
Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This
occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facili-
tate testing of other devices in the scan path.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is
loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and
I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and
are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because
the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents
while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will
not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the
TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP
operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then
places the boundary scan register between the TDI and TDO pins.
Select DR
Capture DR
0
Shift DR
Exit1 DR
Pause DR
Exit2 DR
Update DR
1
Select IR
Capture IR
0
Shift IR
Exit1 IR
Pause IR
Exit2 IR
Update IR
1
Test Logic Reset
Run Test Idle
0
1
0
1
1
0
1
1
1
0
0
1
1
0
0
0
0
1
1
0
0
0
0
0
1
1
1
1
相關PDF資料
PDF描述
GS8644ZV36E-200I 72Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8644ZV36E-225 72Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8644ZV36E-225I 72Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8644ZV36E-250 72Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8644ZV36E-250I 72Mb Pipelined and Flow Through Synchronous NBT SRAM
相關代理商/技術參數
參數描述
GS8644ZV36E-200I 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 72MBIT 2MX36 6.5NS/2.7NS 165FBGA - Trays
GS8644ZV36E-225 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 72MBIT 2MX36 6.5NS/2.5NS 165FBGA - Trays
GS8644ZV36E-225I 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 72MBIT 2MX36 6.5NS/2.5NS 165FBGA - Trays
GS8644ZV36E-250 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 72MBIT 2MX36 6.5NS/2.3NS 165FBGA - Trays
GS8644ZV36E-250I 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 72MBIT 2MX36 6.5NS/2.3NS 165FBGA - Trays
主站蜘蛛池模板: 泗水县| 贡嘎县| 阜南县| 印江| 吉林市| 万州区| 襄垣县| 浮梁县| 大同市| 九寨沟县| 砚山县| 桦南县| 和田县| 宁化县| 萨迦县| 沛县| 香格里拉县| 泰州市| 大余县| 汝州市| 大荔县| 新晃| 滨海县| 东乌珠穆沁旗| 德兴市| 贡山| 大荔县| 丁青县| 永福县| 富源县| 金堂县| 沂水县| 丹东市| 都兰县| 紫金县| 儋州市| 大兴区| 防城港市| 文水县| 施秉县| 乌审旗|