欧美成人免费电影,国产欧美一区二区三区精品酒店,精品国产a毛片,色网在线免费观看

參數(shù)資料
型號(hào): GS8662D08GE-333I
廠商: GSI TECHNOLOGY
元件分類(lèi): DRAM
英文描述: 72Mb SigmaQuad-II Burst of 4 SRAM
中文描述: 8M X 8 DDR SRAM, 0.45 ns, PBGA165
封裝: 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165
文件頁(yè)數(shù): 23/29頁(yè)
文件大小: 896K
代理商: GS8662D08GE-333I
Preliminary
GS8662D08/09/18/36E-333/300/250/200/167
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.01a 2/2006
23/29
2005, GSI Technology
Hold Times
Address Input Hold Time
t
KHAX
0.4
0.4
0.5
0.6
0.7
ns
Control Input Hold Time
t
KHIX
0.4
0.4
0.5
0.6
0.7
ns
Data Input Hold Time
Notes:
1.
All Address inputs must meet the specified setup and hold times for all latching clock edges.
2.
Control singles are R, W, BW0, BW1, and (NW0, NW1 for x8) and (BW2, BW3 for x36).
3.
If C, C are tied high, K, K become the references for C, C timing parameters
4.
To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus contention because tCHQX1 is a MIN param-
eter that is worst case at totally different test conditions (0
°
C, 1.9 V) than tCHQZ, which is a MAX parameter (worst case at 70
°
C, 1.7 V). It is not possible for two SRAMs on the
same board to be at such different voltages and temperatures.
5.
Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
6.
V
DD
slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once V
DD
and input clock are stable.
7.
Echo clock is very tightly controlled to data valid/data hold. By design, there is a ±0.1 ns variation from echo clock to data. The datasheet parameters reflect tester guard bands
and test setup variations.
t
KHDX
0.28
0.3
0.35
0.4
0.5
ns
AC Electrical Characteristics (Continued)
Parameter
Symbol
-333
-300
-250
-200
-167
Units
Notes
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
相關(guān)PDF資料
PDF描述
GS8662D09E-167 72Mb SigmaQuad-II Burst of 4 SRAM
GS8662D09E-167I 72Mb SigmaQuad-II Burst of 4 SRAM
GS8662D09E-200 72Mb SigmaQuad-II Burst of 4 SRAM
GS8662D09E-200I 72Mb SigmaQuad-II Burst of 4 SRAM
GS8662D09E-250 72Mb SigmaQuad-II Burst of 4 SRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS8662D09BD-300 制造商:GSI Technology 功能描述:165 FBGA - Bulk
GS8662D09E-167 制造商:GSI 制造商全稱(chēng):GSI Technology 功能描述:72Mb SigmaQuad-II Burst of 4 SRAM
GS8662D09E-167I 制造商:GSI 制造商全稱(chēng):GSI Technology 功能描述:72Mb SigmaQuad-II Burst of 4 SRAM
GS8662D09E-200 制造商:GSI 制造商全稱(chēng):GSI Technology 功能描述:72Mb SigmaQuad-II Burst of 4 SRAM
GS8662D09E-200I 制造商:GSI 制造商全稱(chēng):GSI Technology 功能描述:72Mb SigmaQuad-II Burst of 4 SRAM
主站蜘蛛池模板: 凤阳县| 通渭县| 东阿县| 肥乡县| 云林县| 北宁市| 东海县| 延安市| 丰台区| 岗巴县| 太保市| 衡东县| 丰镇市| 垣曲县| 三门峡市| 东至县| 塘沽区| 黄石市| 渭南市| 光山县| 汤阴县| 自贡市| 寻乌县| 夏邑县| 丹凤县| 平山县| 元朗区| 荃湾区| 东辽县| 诸暨市| 富锦市| 鹤峰县| 孝义市| 门头沟区| 淄博市| 灵璧县| 南平市| 鹤岗市| 新营市| 沛县| 岳西县|