欧美成人免费电影,国产欧美一区二区三区精品酒店,精品国产a毛片,色网在线免费观看

參數資料
型號: GS8662D18E-167
廠商: GSI TECHNOLOGY
元件分類: DRAM
英文描述: 72Mb SigmaQuad-II Burst of 4 SRAM
中文描述: 4M X 18 DDR SRAM, 0.5 ns, PBGA165
封裝: 15 X 17 MM, 1 MM PITCH, FPBGA-165
文件頁數: 1/29頁
文件大小: 896K
代理商: GS8662D18E-167
Preliminary
GS8662D08/09/18/36E-333/300/250/200/167
72Mb SigmaQuad-II
Burst of 4 SRAM
333 MHz–167 MHz
1.8 V V
DD
1.8 V and 1.5 V I/O
165-Bump BGA
Commercial Temp
Industrial Temp
Rev: 1.01a 2/2006
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
1/29
2005, GSI Technology
Features
Simultaneous Read and Write SigmaQuad Interface
JEDEC-standard pinout and package
Dual Double Data Rate interface
Byte Write controls sampled at data-in time
Burst of 4 Read and Write
1.8 V +100/–100 mV core power supply
1.5 V or 1.8 V HSTL Interface
Pipelined read operation
Fully coherent read and write pipelines
ZQ pin for programmable output drive strength
IEEE 1149.1 JTAG-compliant Boundary Scan
Pin-compatible with present 9Mb, 18Mb, and 36Mb and
future 144Mb devices
165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
RoHS-compliant 165-bump BGA package available
SigmaQuad
Family Overview
The GS8662D08/09/18/36E are built in compliance with the
SigmaQuad-II SRAM pinout standard for Separate I/O
synchronous SRAMs. They are 75,497,472-bit (72Mb)
SRAMs. The GS8662D08/18/36E SigmaQuad SRAMs are
just one element in a family of low power, low voltage HSTL
I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking systems.
Clocking and Addressing Schemes
The GS8662D08/09/18/36E SigmaQuad-II SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer. The device also allows the user to manipulate the
output register clock inputs quasi independently with the C and
C clock inputs. C and C are also independent single-ended
clock inputs, not differential inputs. If the C clocks are tied
high, the K clocks are routed internally to fire the output
registers instead.
Because Separate I/O SigmaQuad-II B4
RAMs always transfer
data in four packets, A0 and A1 are internally set to 0 for the
first read or write transfer, and automatically incremented by 1
for the next transfers. Because the LSBs are tied off internally,
the address field of a SigmaQuad-II B4
RAM is always two
address pins less than the advertised index depth (e.g., the 4M
x 18 has a 1024K addressable index).
Parameter Synopsis
- 333
-300
-250
-200
-167
tKHKH
3.0 ns
3.3 ns
4.0 ns
5.0 ns
6.0 ns
tKHQV
0.45 ns
0.45 ns
0.45 ns
0.45 ns
0.50 ns
165-Bump, 15 mm x 17 mm BGA
1 mm Bump Pitch, 11 x 15 Bump Array
Bottom View
相關PDF資料
PDF描述
GS8662D18E-167I 72Mb SigmaQuad-II Burst of 4 SRAM
GS8662D18E-200 72Mb SigmaQuad-II Burst of 4 SRAM
GS8662D18E-200I 72Mb SigmaQuad-II Burst of 4 SRAM
GS8662D18E-250 72Mb SigmaQuad-II Burst of 4 SRAM
GS8662D18E-250I 72Mb SigmaQuad-II Burst of 4 SRAM
相關代理商/技術參數
參數描述
GS8662D18E-167I 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb SigmaQuad-II Burst of 4 SRAM
GS8662D18E-200 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb SigmaQuad-II Burst of 4 SRAM
GS8662D18E-200I 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb SigmaQuad-II Burst of 4 SRAM
GS8662D18E-250 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb SigmaQuad-II Burst of 4 SRAM
GS8662D18E-250I 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb SigmaQuad-II Burst of 4 SRAM
主站蜘蛛池模板: 荆州市| 塘沽区| 建平县| 泗洪县| 沐川县| 福清市| 惠来县| 定襄县| 东海县| 津南区| 湘潭县| 广宁县| 孟津县| 阿克苏市| 尖扎县| 通城县| 九龙城区| 织金县| 沧州市| 灌阳县| 乌苏市| 瑞金市| 雷波县| 岳普湖县| 枣强县| 磐安县| 祁阳县| 岳池县| 青龙| 黔江区| 边坝县| 河北区| 柞水县| 和平区| 同心县| 桂林市| 奉贤区| 玛纳斯县| 开平市| 遵化市| 普格县|